Signal declaration doubt

[priya23]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vari is
port(a,b,c:in integer;
d,eut integer);
end vari;
architecture df of vari is
signal j:integer:=0;
begin

j<=j+2;
e<=j;

process(a)
variable k:integer:=0;
begin
k:=k+1;
d<=k;
end process;
end architecture;




hre i check e value....
so in my first run of simulation e=9996,j=9998.hw the j is 9998.i declare initially j as zero.then hw j is showing 9998.actually j must be 1 at the time of simulation.anyone knw abt this pls rply

 

[scanman]

Hi,

Remember the initialization value for "j := 0" is set only once at the beginning when FPGA is reset.
"k" will start at 0 every time that process is executed. If you need j to start at 0 then you will need
to make a reset process for it.

scanman

 

[FvM]

A signal assignment without timing control will repeat each simulator timestep, e.g. 1 ps or 1 ns. The VHDL "program" won't be synthesizable in hardware at all.

If you intended more than a curious result, you should start with VHDL examples from a text book or tutorial.

 

[permute]

j <= j+2; outside of a process doesn't make much sense. it is a combinatorial loop -- the value of j cannot be determine. after all, if j = 0 then j=2. but if j=2 then j=4. but if j=4 then j=6. without a concept of time/memory, j will just be continually updated.

done inside of a clocked process it would be valid. wait 1 clock, j becomes 2. on the next clock, 4. on the next clock, 6.