Row and Column address counter

[maulin sheth]

Hello all,

Can anyone help me to understand what is Row and Column address counter in the SRAM?

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Thanks & Regards,
Maulin

 

[ThisIsNotSam]

I am not familiar with the use of the word counter in this context. Are you writing a testbench? Otherwise we refer to address only, which is then decoded to access the correct rows and columns of the SRAM bitcell array.

 

[maulin sheth]

Thanks.
I am not writing out the testbench but I am looking for a fundamental things.
Like Does all memories support the row and column address counter? Or only specific memory have a both access. I know that most of the memories have a column address counter.But looking for information regarding both i.e. column/row address counter.

 

[FvM]

No, there's no counter involved in SRAM design, just row and column address decoder. Where did you get the idea?

 

[ThisIsNotSam]

No, there's no counter involved in SRAM design, just row and column address decoder. Where did you get the idea?

I am lost here too, OP is not a native speaker and must be translating it wrong.