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Routing congestion occurs if number of available routing tracks are less than number of required routing tracks...,to avoid that routing congestion the gcells having higher routing tracks can be moved to gcells having less routing tracks(i.e, by spreading)....., the top level layers are for power analysis,and after that clock and after that for standard cell pins are connected to lower metals(metal 1 and in some cases metal 2 also)...,
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