Representation in big endian form using vhdl

[cristiano7]

Hi, i want to do a silly question..i have a signal len1<="1000" and i wonna represent this signal to a new signal len2 which is 128 bit in big endian form...so the len2(0 to 127) will be "0...0(123)1000"! am i right?

 

[FvM]

The term big endian (or little endian) designates the byte order in byte oriented processors and doesn't fit for VHDL bit vectors. The technical term is ascending and descending array range. Predefined numerical types like signed and unsigned are restricted to descending ranges by convention.

Referring to your example, you didn't tell the bit order of signal len1. Also you can't assign bit vectors of different length directly. Bit vectors of same length are assigned according their "left to right" order, independent of ascending or descending. If you want to keep the "high to low" order, you must perform a bitwise assignment.

 

[cristiano7]

i don't have understood totally what you said ,however i hope that i can be more clear with the next.
len1(0 to 3)<="1000";
To be more specific in my case i have a task that says the following:
You have a message M which is len1 bits.(So let's say that M(0 to 7)<="11001100" and thus len1(0 to 3)<="1000").Append the bit 1 to the end of the message M followed by 384-1-len1mod512 of zeros(len1 here at its integer form of course,so len1 here is 8).And now is the part that i am confused a bit.It says append the 128-bit block that is equal to the number len1(so here it means the number 8)expressed using a binary representation in big endian form.

So in the case :
M(0 to 7)<="11001100";
len1(0 to 3)<="1000";
the outcome according to the previous would be:
out(0 to 511)<="1100110010..0(383)0...01000";
Am i more clear now?

 

[FvM]

How do you know, that len1(0 to 3)<="1000" represents the integer number 8? Unless you're referring to a VHDL library, that defines a respective representation, no integer number can be related to an ascending order std_logic_vector.

 

[cristiano7]

the length of the message M(which is "11001100") is 8 bits, right?So the binary representation of the length of the message is "1000",isn't it?Integer 8 is "1000"(1000=8).So why should it be wrong that len1(0 to 3)<="1000" represents the integer number 8?No i do not have a vhdl library for the matching of the length of the message and the len1 parameter(if this is what you mean)!do you agree that the outcome should be: out(0 to 511)<="1100110010..0(383)0...01000" according to the task ?If not what do you believe?Thanks again for your interest to my question!

edit:" no integer number can be related to an ascending order std_logic_vector."
the task says to represent the length in binary form.So i need an std_logic_vector to represent the binary form (which is 1000).why should i use the vhdl library that you refer to?What i want is to make the out(0 to 511) signal as i want and not to make the vhdl system to understand why 1000 is 8!But firstly is the out(0 to 511) signal right according to the task ?Is it right?

 

[TrickyDicky]

"1000" is 8 in unsigned binary, but -8 in signed binary. or it could be 1 if you were taking the right most bit as the MSB if you use the range 0 to 3.
So this is why we stick to using downto, rather than to for a start.

This is the flaw in using std_logic_vector to represent an integer. Theres no qualification whether it is signed or unsigned.

 

[cristiano7]

ok, so what do you advise me to do ?

 

[FvM]

So why should it be wrong that len1(0 to 3)<="1000" represents the integer number 8?

It's not wrong, but opposite to the number representation of existing numerical VHDL libraries. If you cast it to unsigned(3 downto 0), the integer value is 8.

Using ieee.numeric_std, the expression is

to_integer(unsigned(len1))

Append the bit 1 to the end of the message M followed by 384-1-len1mod512

Followed by 384-1-len1mod512 of what?

 

[cristiano7]

Followed by 384-1-len1mod512 of zeros('0').

 

[cristiano7]

see the following for example.Here we have the message M<="011000010110001001100011" and the length of the message M is 24 bits.(here we have the out(0 to 1024) signal, something similar but it follows the same rule for the representation of the length of the message ).As you can see number 24 (which is "11000") is represented as 0...011000.(As i mentioned before for the case of 8 which i wrote it as 0....01000)

 

[TrickyDicky]

you're really not being very clear about what you are doing. Why do you need a 512bit word? why cant you just generate it on the fly using a state machine?

I suggest you post what you're actually trying to acheive or some code you've come up with already.

FvM: using ascending ranges for numeric_std is fine, it treats the 0 as the MSB, but functions will always return downto arrays, but these can be assigned to asscending arrays.

---------- Post added at 10:17 ---------- Previous post was at 10:14 ----------

The picture you have attached makes no sense because there is no context? what kind of message is it? what you are sending it to? how are you transmitting it? what do "a" "b" and "c" mean? are they control characters?

And then what is wrong with an output(1023 downto 0) as the output? how do you expect to map such a large array to anything else?

 

[cristiano7]

what i wanna do is exactly what the task above demonstrates!
You have a message M which is l bits.(So let's say that M(0 to 7)<="11001100" and thus len1(0 to 3)<="1000",len1 represents the length of the message in bits).Append the bit 1 to the end of the message M followed by 384-1-lmod512 of zeros( l here is 8).And now is the part that i am confused a bit.It says append the 128-bit block that is equal to the number l(so here it means the number 8)expressed using a binary representation in big endian form
this is my code for the message M padding:

signal message1: std_logic_vector(0 to 7);
signal len1: std_logic_vector(0 to 3);
signal message2: std_logic_vector(0 to 511);

message1<="11001100";
len1<="1000";
process (message1,len1)
begin
for i in 0 to 7 loop
message2(i)<=message1(i);
end loop;
message2(8)<='1';
for i in 9 to 383 loop
message2(i)<='0';
end loop;
for i in 384 to 507 loop
message2(i)<='0';
end loop;
for i in 508 to 511 loop
message2(i)<=len1(i-508);
end loop;

end process;

here message2 is the out(0 to 511) signal that i talked about above!

---------- Post added at 10:25 ---------- Previous post was at 10:22 ----------

a,b,c are 8-bit ASCII character.Not hex!The message2 signal is being xored with an other std_logic_vector!

 

[TrickyDicky]

you code doesnt really demonstrate anything other than setting three constants. And hex is just hexadecimal, so a, b and C can be represented in hex as "61", "62", "63".

and why did you use so many loops, why didnt you just write this?

message2(0 to 7)     <= message1;
message2(8)          <= '1';
message2(9 to 383)   <= (others => '0');
message2(508 to 511) <= len1;

There is no need for a process.

Where is your output?

---------- Post added at 10:35 ---------- Previous post was at 10:31 ----------

Plus, you still havent explained what the message is for? is it some transmission protocal? and how is the message transmitted?

 

[cristiano7]

message2 is a signal which i use for a xor gate with another std_logic_vector called hi.so i do after that:
message2 xor hi.So i don't have to make message2 as an output.I need it as a signal!

 

[FvM]

O.K. An what's the problem now? I guess, it's about changing the code to variable length message. But you have defined message1 with a fixed length of 8. So at best, you can make it work for a variable message length of 0 to 8.

But apart of this problem, you can use an integer variable len:=to_integer(unsigned(len1)) instead a fixed length of 8 in all loop expressions and get the variable length operation. You can simplify the code by preloading (others => '0') to message 2 and only filling the non-zero part.

 

[cristiano7]

"I guess, it's about changing the code to variable length message. But you have defined message1 with a fixed length of 8. So at best, you can make it work for a variable message length of 0 to 8. " --Yes this is one thing that i have in my mind to solve sometime, but not now.Now i really have to certify that the padding of the message1 is right.
To make things simpler, i want to give as an input a message1 , the length of the message1 and the system should use those to make the message2 which would be: message2<=message1&1&0000....000&(128-bit binary representation of the length of the message1 in big endian form)...

 

[TrickyDicky]

so whats the question?

 

[cristiano7]

So in the case :
message1(0 to 7)<="11001100";
l<=8(which is the length of the message1)
the outcome according to the previous would be:
message2(0 to 511)<="1100110010..0(383)0...01000";???????

 

[TrickyDicky]

with your code, yes.

 

[cristiano7]

i know that with my code it is right , i can see it on the simulation! I am not sure if it is right according to the task which says : 128-bit binary representation of the length of the message1 in big endian form