sweethomela8
Member level 4
I'm using a Xilinx spartan FPGA and want to write some VHDL where I can register the output (10 bit) of an ADC. I continuously clock the ADC at 50Mhz and the rest of the FPGA runs on the rising edge of the 50Mhz clock, I want to be able to register the ADC data on the falling edge of the clock to ensure data stability. How can this be done easily?
Should I have some registers clock the data on the falling edge and then have rising edge logic register those registers on the rising edge?
thanks in advance.
Should I have some registers clock the data on the falling edge and then have rising edge logic register those registers on the rising edge?
thanks in advance.