RMS voltage calculation strategy for ADC

[sameeksh shetty]

Hi ,
I am using zynq 7020 SOC for my fpga development.
In here there is a ADC device (ADC3660IRSBT) that is connected to fpga.
Few things on ADC configuration:-
1. The sampling rate is 10Mhz
2. Bandwidth we are targeting is 16 bit per channel.
3. We are using ADC in dual channel mode.

Now on FPGA side, we have created a IP for SPI controller. This IP communicated with ADC using spidev to configure,read and write into the spi device.

This has been achieved. We are able to configure the ADC and using the Integrated logic-analyzer we are able to see the data and clock pulse.

Now the next stage is data acquisition and calculation of RMS value. Here we though of storing the data that is coming in to be stored in FIFO block and then the RMS is calculated for the values stored in FIFO. This RMS value is then routed to IO registers.

I was not able to achieve this. I am unsure about this design idea.
So can you please any other way that has already been tried and tested .

Regards,
Sameeksh Shetty

 

[KlausST]

2. Bandwidth we are targeting is 16 bit per channel.

"16 bit" is not a measure of bandwidth. Did you mean resolution? or did you mean Bandwidth (which usually means frequency)

3. We are using ADC in dual channel mode.

What is this? Datasheet doesn´t tell about "dual channel mode"

I was not able to achieve this.

What exactly did you try, what did you expect, and what did you not achieve?

****
What is your RMS calculation method? Fixed widow size? Using low pass filter?
Including DC or excluding DC?
How often is the RMS value calculated? As running RMS after each ADConversion?
What accuracy, precision, resolution fo the output do you expect?
Is the input signal frequency known, or random?
****
RMS basically - as the names says: The ADC values need to be squared, then averaged (or filtered), then the square root is taken.



Klaus

 

[sameeksh shetty]

"16 bit" is not a measure of bandwidth. Did you mean resolution? or did you mean Bandwidth (which usually means frequency)

Yes you are right it is a 16bit ADC.

What is this? Datasheet doesn´t tell about "dual channel mode"

The ADC3660 is a16-bit high-speed dual channel ADC family supporting sampling rates up to 65Msps.(https://www.ti.com/lit/ds/symlink/a...oduct%2FADC3660%2Fpart-details%2FADC3660IRSBT)

What exactly did you try, what did you expect, and what did you not achieve?

I tried to read in the data coming from ADC to a FIFO block(vivado software provided IP was used here[AXI4-STREAM DATA FIFO]).

Now the data end that is going to FIFO is connected to the RMS block (again its a vivado given IP[RMS_CALCULATOR_v1_0]).

The output of the RMS block goes to GPIO.

I am not sure whether this logic will work.I am expecting to see the rms value on the GPIO IO registers.

What is your RMS calculation method? Fixed widow size? Using low pass filter?

Here I am using a RMS block to do the calculation. So I am not sure how this is done.

Including DC or excluding DC?
How often is the RMS value calculated? As running RMS after each ADConversion?
What accuracy, precision, resolution fo the output do you expect?

I am unsure about this too. I will get back with answers for these.

Is the input signal frequency known, or random?

The input voltage frequency given to ADC is 60Hz , 230V.

I will get some more clarity on what is being done here. Thanks for your time.

Regards,
Sameeksh Shetty

 

[KlausST]

Hi,

You need to learn how this RMS block works (I don´t know).
Simply inputting an ADC stream ... and expexcting a meaningful output does not work, because RMS is related to "time" or "number of samples" or "cut off frequency" .. or some other measure of "time".

Maybe (indeed I expect this) there is some parametric setup for theis RMS block.

Klaus

 

[FvM]

I don't understand the purpose of AXI interface and FIFO in your design. If I understand right you have a continuous ADC data stream and want to calculate RMS without previous filtering or decimation. RMS measurement involves a low pass filter (continuous operation) or output sample rate (discontinuous operation) for the output signal.