Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Regarding high third order harmonic in lc vco

Status
Not open for further replies.

bestvlsi

Junior Member level 1
Joined
Jan 8, 2011
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,452
Cadence :- Regarding high third order harmonic in lc vco

Hi all,

Q-1
I am designing an LC VCO in UMC 18 process at 2.5 GHz. While doing PSS analysis I am getting third order harmonic at -43dB whereas the fundamental harmonic at -11dB. Ive read in some paper that the third order harmonic should be atleast 40dB below the fundamental so as to have good noise performance...is this information correct?

Moreover while doing transient analysis , when I am plotting the current at the node of the one of the bottom cross coupled NMOS pair I am getting the current waveform as a distorted one i.e. it is not coming sinusoidal but as if some higher order harmonic is coming into picture giving twin peaks in one cycle(one peak lesser than the other one). I think this is due to the third order harmonic distortion...am I correct? Also I tried to reduce this by using an LC filter at the current mirror (as given in an IEEE paper) this method gives a smooth sinusoidal current waveform at the above mentioned node ... but the problem is in the PSS analysis Iam getting the same performance as without the LC filter (i.e. fundamental harmonic at -11dB and third harmonic at -43dB as I mentioned in the above para...).

Can someone please tell a method where I can reduce the third harmonic component?

Q-2

Do i need to add a resistance in series with the inductance in the LC tank considering the fact that it already has a parasitic resistance..? Will it impact the noise performance/transient current waveform?

Q-3

Also when I plot the current waveform in transient analysis at any one of the cross coupled NMOS pair. I see that I cannot increase the width of the pair beyond 10uM. If I do it then not only the distortion in current waveform increases but also there is heavy over and undershooting of the current (which ideally should swing between 0 and I bias ) . My Ibias is 2.64mA.

Regards.
 
Last edited:

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top