Questions regarding OFFSET voltage

[suraj]

Regarding Offset Voltage

Dear Friends

I have questions related to the OFFSET voltage

1. Which is the main contributor of the OFFSET voltage of the differential amplifier, input devices or the load devices?

2. To reduce the OFFSET voltage when designing the circuit what aspect ratio do we select among the following

a) Large W/L, W.L, or
b) Large W and constant L or
c) Large L and constant W.

Thanks a lot for your help

Suraj

 

[djalli]

Regarding Offset Voltage

1. Both!
Depedends on situation which is the main contributor. Please be specific in case!

2. To reduce offset voltage (an most of cases is DC value) you add a high-pass filter or DC blocking capacitor.

Is that what yu needed?

 

[suraj]

Re: Regarding Offset Voltage

Thanks Djalli for your reply,

In the case of the pramplifier of Comparator, in that case which devices contribute more offset, input or load devices ?

Input devices are NMOS and Load devices are Diode connected(G&D connected) PMOS devices.

Thanks
Suraj

 

[krashkealoha]

Re: Regarding Offset Voltage

Offset is reduced if you can go with a larger L & W. What will limit the size you can use is your bandwidth requirement for the comparator because increasing either L or W will degrade bandwidth performance.

Another thing that will help, is to use common-centriod layout design (assuming you are designing a IC).

 

[mady79]

Re: Regarding Offset Voltage

Offset comprises of sytematic and random offset .Systematic offset is due to the mismatch between the dc bias point voltages (at the differential output nodes ) and random offset is due to the mismatch in delta Rload,delta threshold voltage and delta dieelectric .

Techiques to reduce the offset in design & layout phase :
1)Make sure that the design has high DC gain as this would reduce the input referred offset considerably.
2)Bias the load pmos properly to reduce the systematic mismatch (make the VDS of the load equal )
3)High gm for the input pair would reduce the input referred offset than high ro of the load .
4)Pelgrom's paper make's it clear that offset is indirectly proporational to of area of the MOS (W*L) and directly proportional to the placement distance between the transistor's .So one can properly place transistor 's which need to matched and use common centroid layout to reduce the gradients but this comes with added parasitics .

 

[alastair41]

Re: Regarding Offset Voltage

Besides the techniques in designing a low offset opamp, you might want to try some external or higher level design methods to eliminate the opamp offsets. For example, you might want to try input offset cancellation, output offset cancelaation, etc. Good luck.

 

[kyrandia]

Re: Regarding Offset Voltage

For differential opamp of hign gain, the offset mainly come from input pair and load.
To reduce input pair's effect, large effective area and little Vgs-Vth are important.
To reduce load's effect,large effective area and large Vgs-Vth are important.

 

[sunking]

Re: Regarding Offset Voltage

One of effective way is big size input transistor and load transistor.
An other is chopper OPA.

 

[opamp741]

Re: Regarding Offset Voltage

Here is some offset calculation (assuming offset is due to Vt mismatch):
Vt(mismatch)=(AVtn^2/Wn.Ln+(Gmp/Gmn)*AVtp^2/Wp.Lp)^0.5
This is for a diffamp with n type input device..
AVtn and AVtp are constants depends on process..may be available in ur technology information file..
regards

 

[Owen Hao]

Re: Regarding Offset Voltage

Do you read the textbook, "Design of Analog circuit and system", edited by Laker?
There are clear descriptions about the offset voltage in the chapter 6.
It will help you very much, I think.

 

[sunking]

Regarding Offset Voltage

swith cap can reduce the offset much!

 

[Syukri]

Re: Regarding Offset Voltage

What is that switch cap?

Isn't transistor is a switch itself and also got capacitance?

CAn I get an explaination..I'm doing something similar like this also