[Questasim] why UVM simulation is too slow?

[yuhiub90]

Guys,

I'm running normal (without UVM, SVA, functinal coverage, code coverage) simulation and UVM simulation on the same testcase. But UVM simulation takes so much of time comparing with normal simulation. What's the causes of this strange behavior? Please help me to figure this out.

Thanks

 

[dave_59]

I think you answered your own question. You have no idea what your UVM testbench is doing. How is anyone supposed to help you?

 

[yuhiub90]

Dave, I'm not specialize in verification. I just want a brief explanation for this. I guest the SVA check, code coverage and functional coverage calculation during simulation slow it down. Please confirm it for me.

Thanks

 

[dave_59]

Code coverage performance is easy to explain. With no modification to your source code, you add a switch to your simulation and it adds a lot extra calculations that will slow your simulation down. You do not want to run with code coverage turned on for every simulation. Only after your test is passing, and then only periodically in regression tests.

You didn't explain the difference between a normal simulation and a UVM simulation. Is it the same stimulus and the UVM is just added to monitor and check the results? When you add code to a simulation, that will slow down the performance of the simulation depending on how much code was added, and how efficiently that code was written. Sometime a very few poorly written constructs like an assertion can slow down your simulation a lot. Questa has profiling tools to help you find those constructs.

If the UVM simulation is providing different stimulus than a normal simulation, then you can't make a fair comparison without knowing what parts of the design are being exercised, and how long the testcase is running for.

 

[yuhiub90]

Yes, UVM simulation uses same stimulus as normal simulation but with UVM added. Thanks Dave, it helps.

 

[rexjohn4u]

Hello Yuhiub90,

I wonder with your finding about UVM. Anyway compilation may take bit more time than system verilog tb(again you won't find the time difference) But simulation depends on your tb and what stimulus you are exercising. If you think stimulus is same for both sv and UVM tb, then you may not have dropped any objection somewhere. Please check this
Again if at all you haven't dropped it, simulation wont end unless you have provided max time out.
Your query is incomplete. So cant bring out a proper solution.