Query regarding wire and reg

[pratibha m d]

Hi All,

I am not able to understand the difference b/w wire and reg when it comes to synthesis. What I understand is that, a reg stores a value when an even occurs on signals in its sensitivity list while a wire is continuously assigned.
I have come across a shift register code, a snap shot of which I have attached with this mail. The snap shot also shows the RTL view of the shift reg in which I am not able to notice the difference b/w wire and reg, and also the RTL view for ascending and descending part of the variable.
Plz help me in understanding this.



Thanks

 

[light]

The point is that you need to understand the difference between the blocking assignment and the unblocking assignment statement.

The assignment happens immediately in the blocking assignment statement. In my opinion, it blocks the other statement to execute unless it finished.

while in the unblocking assignment statement, all statement execute at the same time and the assignment happened at the end of the always statement.

 

[sudhirkv]

In the snapshot u have provided there is no wire at all.
all the variables declared are reg.

when thinking of synthesis,

a wire is just a connection between two variables or signals.

say a clock signal. there is one clock port and u have to connect clock signal to all the registers. so u need a wire to connect all the registers.

so a wire cannot save or store a signal. its just a wire to connect the signals, and its not dependent on any signal. whatever comes to that wire its going to transfer.

But reg can stores a value and its fully dependent on clock and data. in the example in the snapshot he has written a code for shift register. what he is trying to explain is the dfference between bocking and non blobking statement.

if u simulate the design in modelsim,u will get the correct output but not in the case of synthesis. bcoz modelsim knows that it is a for loop and it has its own internal registers to store its intermediate varaibles, but synthesis tool will consider this as process which has to be completed in one single clock and it will assign assign the values all in one shot since there is no register to store the intermediate value.