quadrature decoder - VHDL code

[sanishvsanu]

quadrature decoder

I have to impliment a Driver support system for automobiles.now i have to determine velocity,acceleration,position etc using Quadrature decoder.my code is here and please include the portion for calculate the above.am using Nios 2 development board for cyclone 2 fpga.

QUAD.Vhdl

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;

entity counter is
--GENERIC (n: integer :=50000000);
Port ( Clk : in std_logic;
A_In : in std_logic;
B_In : in std_logic;
up_down :buffer std_logic;
data_out : out std_logic_vector(3 downto 0);
Dir : buffer std_logic;
Reset : in std_logic);
--s : buffer std_logic);

end counter;
architecture Behavioral of counter is
SIGNAL Last_A, Last_B :std_logic;
SIGNAL Current_A, Current_B : std_logic;

SIGNAL count:std_logic_vector(3 downto 0) :="0000";
begin
up_down <= (Current_A xor Last_A) xor (Current_B xor Last_B);
Dir <= Current_A xor Last_B;
--up_down <= '1';

--Dir <= Last_B xor Current_A;
-- countingROCESS (clk)
-- VARIABLE f : INTEGER range 0 to n+1 ;
-- begin
-- if (clk'event and clk='1') then
-- f:=f+1;
--
-- if ( f>=n/2 and f<n) then
-- s<='1';
-- elsif ( f=n) then
-- s<='0';
-- f:=0;
-- end if;
-- end if;
-- end process counting;


process (clk, Reset)
begin
if Reset = '1' then
Last_A <= '0';
Last_B <= '0';
Current_A <= '0';
Current_B <= '0';
elsif rising_edge(clk) then
Last_A <= Current_A;

Last_B <= Current_B;


Current_A <= A_In;

Current_B <= B_In;


end if;
end process;

process (clk, Reset) begin
IF (Reset = '0') THEN
count <= "0000";

ELSIF (clk'EVENT AND clk= '1')THEN

IF(up_down = '1') THEN
IF(Dir='1')THEN
count <= count + 1;
ELSIF(up_down = '0') THEN
IF(Dir='0')THEN
count <= count - 1;
END IF;
END IF;
END IF;
END IF;
data_out <= count;
END PROCESS;

end Behavioral;