Q: XC95144XL VHDL inout

[TheBorg]

Hi.

I have now for some time tried to use the WebPack simulator from Xilinx, i have defined a port as inout port (databus for a SRAM), there is no problems writing to the port, but i cant get it to work when trying to read from the port according the simulator.

I have added the simple test code, which i have testet the inout with, with the code below a cant read from the databus, so if anybody body has an idear what i am doing wrong here ?


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Counter is
Port ( EXT_SYS_Clock : in std_logic;
EXT_SRAM_Data : inout std_logic_vector(7 downto 0);
EXT_LATCH_Data : out std_logic_vector(7 downto 0));
end Counter;


architecture Behavioral of Counter is
TEST: process (EXT_SYS_Clock)
begin
if (EXT_SYS_Clock' event and EXT_SYS_Clock = '1') then
EXT_SRAM_Data <= "ZZZZZZZZ";
EXT_LATCH_Data <= EXT_SRAM_Data;
end if;

end process;

end Behavioral;




Thanks for your help in advance.

Best regards

René

 

[nand_gates]

This is common problem all VHDL beginner face! The solution is simple;
In the testbench when you are trying to read data you are suppose to drive
"ZZZZZZ" on data bus, and when you are writing data to you drive the inout
bus with data!

 

[TheBorg]

Hi

Thanks for your answer, but it looks like i still have a quistion, i allready in the source for my example put 'zzzzzzzz' on the bus to change for read, but as i have u nderstood i allso have to do it in the testbench ?

I use the 'Generate Expected Simulation Results' and i relly have tried to find where to put the 'zzzzzzzzz' on the bus in the testbench but without any look, the only to stte a can put on is for now '1' and '0' ?

Thanks for your elp in advance.

Best regards

René