salim.alam2
Junior Member level 3
Hi
I hope you are doing well
Actually, I am beginner in VHDL and FPGA, and I will be grateful to you if you can help me.
I have a code in VHDL and I should:
a. Modify the VHDL code of the calculator circuit:
(i) To include a flip operation that complements all bits in dReg.
(ii) To detect arithmetic error conditions. An unsigned addition results in an
arithmetic error if it produces a sum that is too large to fit in the register
used by the calculator (note that the calculator uses a 16 bit register).
Whenever an error is detected, the calculator should set an internal error
bit. The error bit should be cleared when a clear operation is performed
and no other operations should be allowed to occur while the error bit is
set.
for the following code:
I hope you are doing well
Actually, I am beginner in VHDL and FPGA, and I will be grateful to you if you can help me.
I have a code in VHDL and I should:
a. Modify the VHDL code of the calculator circuit:
(i) To include a flip operation that complements all bits in dReg.
(ii) To detect arithmetic error conditions. An unsigned addition results in an
arithmetic error if it produces a sum that is too large to fit in the register
used by the calculator (note that the calculator uses a 16 bit register).
Whenever an error is detected, the calculator should set an internal error
bit. The error bit should be cleared when a clear operation is performed
and no other operations should be allowed to occur while the error bit is
set.
for the following code:
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Library IEEE; USE IEEE.std_logic_1164.all; USE IEEE.numeric_std.all;[CODE][/CODE] Entity calculator is Port ( clk : in std_logic; -- clock Clear, load, add : in std_logic; -- operation signals Din : in std_logic_vector (15 downto 0); -- input data Result : out std_logic_vector (15 downto 0)); -- output data End calculator Architecture a1 of calculator is Signal dReg : std_logic_vector (15 downto 0); Begin Process (clk) Begin If rising_edge (clk) then If clear =’1’ then dReg <= ”0000000000000000”; elsif load=’1’ then dReg <= din; elsif add=’1’ then dReg <= std_logic_vector(unsigned(dreg) + unsigned(din)); --values of dreg and din are converted to unsigned type with unsigned() function. --the unsigned values are added --the result is converted to standard logic vector with std_logic_vector() function. end if; end if; en process; result <= dreg; end a1;
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