problem with the vhdl code..

[reef88]

hi,


i have a problem to combine with this vhdl code.
In xilinx ISE it say unexpected COMPONENT and unexpected TOKOUT.
what this mean?

this is the code:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity VGA_TOP is
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
EN : in STD_LOGIC;
SW : in STD_LOGIC_VECTOR (2 downto 0);
R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
H_S : out STD_LOGIC;
V_S : out STD_LOGIC);
end VGA_TOP;

architecture Behavioral of VGA_TOP is

signal CLK_DIV:std_logic;
signal V_DONE:std_logic;
signal H_CNT:std_logic;
signal COUNT:std_logic_vector (9 downto 0);
signal V_COUNT:std_logic_vector (9 downto 0);
signal H_D:std_logic;
signal V_D:std_logic;
signal COLOR:std_logic;





begin



COMPONENT clknew2
PORT(
CLK : IN std_logic;
CLK_DIV : OUT std_logic
);
END COMPONENT;

Inst_clknew2: clknew2 PORT MAP(
CLK =>CLK ,
CLK_DIV =>CLK_DIV
);

COMPONENT linecontrol
PORT(
CLK_DIV : IN std_logic;
EN : IN std_logic;
RST : IN std_logic;
V_CNT : IN std_logic;
H_V_CNT : OUT std_logic;
V_DONE : OUT std_logic;
V_COUNT : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;


Inst_linecontrol: linecontrol PORT MAP(
CLK_DIV =>CLK_DIV ,
EN =>EN ,
RST =>RST ,
V_CNT =>H_DONE ,
H_V_CNT =>H_CNT ,
V_DONE =>V_DONE ,
V_COUNT =>V_COUNT
);


COMPONENT pixelcntr
PORT(
RST : IN std_logic;
CLK_DIV : IN std_logic;
EN : IN std_logic;
H_CNT : IN std_logic;
INT_RST : IN std_logic;
H_DONE : OUT std_logic;
COUNT : OUT std_logic_vector(9 downto 0)
);
END COMPONENT;

Inst_pixelcntr: pixelcntr PORT MAP(
RST =>RST ,
CLK_DIV =>CLK_DIV ,
EN =>EN ,
H_CNT =>H_CNT ,
INT_RST =>V_DONE ,
H_DONE =>H_DONE ,
COUNT =>COUNT
);


COMPONENT FSM_COMP
PORT(
COUNT : IN std_logic_vector(9 downto 0);
V_COUNT : IN std_logic_vector(9 downto 0);
CLK_DIV : IN std_logic;
RST : IN std_logic;
H_D : OUT std_logic;
H_S : OUT std_logic;
V_D : OUT std_logic;
V_S : OUT std_logic
);
END COMPONENT;

Inst_FSM_COMP: FSM_COMP PORT MAP(
COUNT =>COUNT ,
V_COUNT =>V_COUNT ,
CLK_DIV =>CLK_DIV ,
RST =>RST ,
H_D =>H_D ,
H_S =>H_S ,
V_D =>V_D ,
V_S =>V_S
);

COMPONENT DEC
PORT(
H_D : IN std_logic;
V_D : IN std_logic;
COLOR : OUT std_logic
);
END COMPONENT;


Inst_DEC: DEC PORT MAP(
H_D =>H_D ,
V_D =>V_D ,
COLOR =>COLOR
);

COMPONENT MUX4
PORT(
SW : IN std_logic_vector(2 downto 0);
COLOR : IN std_logic;
R : OUT std_logic;
G : OUT std_logic;
B : OUT std_logic
);
END COMPONENT;


Inst_MUX4: MUX4 PORT MAP(
SW =>SW ,
COLOR =>COLOR ,
R =>R ,
G =>G ,
B =>B


);




end Behavioral;

---------- Post added at 05:20 ---------- Previous post was at 05:17 ----------

can someone in this forum help me please...

 

[Chops211]

The problem is you need to instantiate components before the "begin" and port map after the begin

Good luck

 

[permute]

specifically, there is a difference between component declarations and component instantiations. the "component X is port(...); end component;" is a declaration. This goes either in a package, or before the "begin". The "u_inst : component X port map(...);" is the instantiation. These go after the "begin".