problem in state transitions

[JoseNaveen]

hi..i have written a code for a control unit to be used in my project.. when i simulate it i'm having some problems with the state transitions.. for eg., there is a state transition from state g1 to state c even though it is not possible under the code i have written..i have attached the vhdl files and the test bench..can sumone pls help me with this..?

 

[scanman]

Hi,

Try disabling the following line:

process(curr_state,ur,ack,cw,tx_rdy)
begin
next_state<=curr_state; <<<<< ******** Is this required ?
case curr_state is
when A =>

See this reference on state machines:

**broken link removed**

You could also try setting "next_state" to "A" on initialization.

scanman

 

[permute]

i haven't read the other lines of code, but the next_state <= curr_state is a fairly common line used to prevent latches as well as the need to place the next_state <= curr_state at multiple places inside the case statement. In VHDL, the last nonblocking assign reached will be the one that is used.

 

[JoseNaveen]

i have tried setting next_state to A but no use..still getting the same thing..i'm kinda urgent..::-?

 

[permute]

Does the design meet timing? Does the state machine has async inputs? These two issues can corrupt a state machine.

for sim, you need to add rdbit, urt, ect... to the sensitivity list. basically anything in an "if (expression) then", or anything on the right-hand side of an assignment.

 

[TrickyDicky]

Id go with permute. If any of the signals in that sensitivity list are asynchronous then if they change between clock edges your state machine is going to go haywire jumping through multiple states in a single clock. This is the problem with the 2 process state machine template.

The best thing to do is put it all inside one clocked process. This way you dont need a next_state signal, you just assign the state directly to "current_state" and it can never change more than 1 state per clock.

 

[JoseNaveen]

ya thank u both..i'll try what u have suggested...