problem in implementing state machine in vhdl

[s3034585]

hi guys i am trying to implement a state machine in vhdl. i am just trying to load some shift registers and later shift them in later states.

i have 4 states idle, load, clk_st, compute.
in idle state i try to reset them, in load i load the shift registers with the new values. in clk_st state i shift them once and compute i calculate a value by xoring them and then shift them.
the problem which i am facing is that when it goes into move state it shifts the registers 2 times. i am unable to find out why does it excute this state 2 times.

cany any one please help... i am attaching the code below..
thanks in advance

-----------------------------------------------------------------------------------------------
architecture Behavioral of test is
------------------------------------------------------------------------------

signal c1, c2, c3: std_logic;


type State_Type is (Idle, load , clk_st, compute);

signal Current_State,Next_State: State_Type;

------------------------------------------------------------------------------
begin

statereg: process(Clk,Reset)
begin
if Reset = '1' then
Current_State <= Idle;
elsif (clk'event and clk = '1' )then
Current_State <= Next_State;
end if;
end process;


process ( clk, Current_State,reset)


variable r1_r: std_logic_vector(18 downto 0);
variable r2_r: std_logic_vector(21 downto 0);
variable r3_r: std_logic_vector(22 downto 0);
variable empty_bit: std_logic;

variable cnt : integer;

variable cnt_test : integer;

variable ref_bit: std_logic_vector(64-1 downto 0);
variable shft_reg_r3 : std_logic_vector (2 downto 0);
variable shft_reg_r3_1: std_logic_vector (1 downto 0 );
variable shft_reg_r3_2: std_logic;
variable shft_reg_r3_3: std_logic_vector (2 downto 0 );
begin

case Current_State is
when Idle =>
r1_r := (others=>'0');
r2_r := (others=>'0');
r3_r := (others=>'0');
cnt := 0;
empty_bit:= '0';
fb1 <= '0';
fb2 <= '0';
fb3 <= '0';
c1 <= '0';
c2 <= '0';
c3 <= '0';
shft_reg_r3 := (others=>'0');
shft_reg_r3_1 := (others=>'0');
shft_reg_r3_2:= '0';
shft_reg_r3_3:= (others=>'0');
ref_bit := (others=> '0');
cnt_test := 0;

if load = '1' then
Next_State <= load_reg;
else
Next_State <= idle;
end if;

when load_reg =>
Next_State <= clk_st;
ref_bit := Reference;
r1_r := Vector_In(63 downto 45);
r2_r := Vector_In(44 downto 23);
empty_bit:= r1_r(18) xor r2_r(21) xor ref_bit(Ks_Width-1 );
shft_reg_r3 := "00" & empty_bit ; -- 22 bit
shft_reg_r3_1 := '0' & r3_r(21); --21 bit
shft_reg_r3_2:= r3_r(20); -- 20 bit
shft_reg_r3_3 := "00" & r3_r (7); -- 7 bit

cnt := 1 ;

when clk_st =>
Next_State <= compute;
ref_bit(Ks_Width-1 downto 0) := ref_bit(Ks_Width-2 downto 0)&'0' ;

--"it is shifting ref_bit 2 times... I dont knwo why "

cnt_test:= cnt_test + 1;
empty_bit:= r1_r(18) xor r2_r(21) xor ref_bit(Ks_Width-1 );
shft_reg_r3 := shft_reg_r3(1 downto 0) & empty_bit ; -- 22 bit
shft_reg_r3_1 := shft_reg_r3_1(0) & empty_bit; --21 bit
shft_reg_r3_3 := shft_reg_r3_3(1 downto 0) & r3_r(7); -- 7 bit
shft_reg_r3_2 := empty_bit; -- 20 bit
c1 <= r1_r(8) ;
c2 <= r2_r(10) ;
c3 <= r3_r(10) ;
cnt := 2 ;


when compute =>

Next_State <= compute;

ref_bit(Ks_Width-1 downto 0) := ref_bit(Ks_Width-2 downto 0)&'0';
empty_bit:= r1_r(18) xor r2_r(21) xor ref_bit(Ks_Width-1 );
if (c3 =c1) or (c3=c2) then --2
shft_reg_r3 := shft_reg_r3(1 downto 0) & empty_bit ; -- 22 bit
shft_reg_r3_1 := shft_reg_r3_1(0) & empty_bit; --21 bit
shft_reg_r3_3 := shft_reg_r3_3(1 downto 0) & r3_r(7); -- 7 bit
shft_reg_r3_2 := empty_bit; -- 20 bit

"on one particuar condition it will exit... "
when others =>
null;
end case;

end process;

-------------------------------------------------------------------------------------------

 

[smilermd]

I think that the code for clk_st is shifting once, you receive 2 times shifting because in the next cycle, in the state compute, you are shifting one more time.

compute i calculate a value by xoring them and then shift them

You can't do this in one state, the shift and xor operation happens at the same time.

 

[bansalr]

Remove the clock from the second process. It will help.
Since each state change is two clock cycle . i.e. why it shifts two times.

Make a process either combinatorial or sequential.