Post CMOS process etching

[ahmed edris]

I am working on a design of TEG (thermo electric generator) using cmos process. layout is conducted using cadence but the design needs so called post cmos process etching to create cavity in the substrate. how this information can be delivered to the fab as it would not be included in GDS file.

 

[dick_freebird]

Most likely the CMOS fab will not do this, it would be a
departure from their released and qualified manufacturing
flow.

But there are outfits like IMT who do this all the time for
MEMS and such, also deposition of exotic materials.

I really question the value of using a CMOS flow in any
way for thermoelectric generators. Integrating circuitry
with the thermo elements seems low value, high effort
to me. Hot side of TEG is liable to exceed silicon CMOS
working temp, at least on a non-SOI technology. What
is it that you think makes this a winner?

 

[CMOS-Tangram]

Dear Ahmed,

If you want to etch a zone of your chip in order to make your custom sensor or device you must be sure of this:

First, your design must include an open window in the passivation layer. This provides an access to the volume of oxide or metal that you need to etch before reaching the substrate.

Second, as the open window in the passivation layer, it is important to define a "no-fill area" for the metal dummies, it is usually called "no fill" layer.

If the design does not achieve the design rules you have to inform the foundry that you accept all the risks of fabricating your chip section.

Greetings.