PMOS voltage coupling from S-G during high V transition at S

[kranthi_m]

I am designing a circuit for high voltage applications in low voltage cmos process. In my circuit I have a PMOS whose gate is biassed at VDD-vt with a circuit. Its source has a voltage transition from 0 to 5V in 1ns. Its drain is connected to ground with a high resistance. But the transition at source is increasing the gate voltage. But I need a constant gate voltage irrespective of the transition. How can this be achieved????

Thanks in advance.

 

[erikl]

Re: PMOS voltage coupling from S-G during high V transition

... I need a constant gate voltage irrespective of the transition. How can this be achieved????

You could perhaps arrange for a positive capacitive feed back from the source to the gate. First try with a cap value of about 10*Cgs .

 

[kranthi_m]

Re: PMOS voltage coupling from S-G during high V transition

I tried that. It has two issues.
1. The PMOS is also driven from other circuit. If positive capacitive feedback is used its adding delay while driving .
2. The capacitor is consuming a lot of area.

I can compromise with the second issue but the first hinders my performance.

 

[erikl]

Re: PMOS voltage coupling from S-G during high V transition

1. The PMOS is also driven from other circuit. If positive capacitive feedback is used its adding delay while driving.

Of course. Can you provide stronger drive (without more delay)?

... gate is biased at VDD-vt with a circuit.

Or could you relate the gate drive to the PMOS source instead of to VDD ?

 

[timof]

Re: PMOS voltage coupling from S-G during high V transition

I am designing a circuit for high voltage applications in low voltage cmos process. In my circuit I have a PMOS whose gate is biassed at VDD-vt with a circuit. Its source has a voltage transition from 0 to 5V in 1ns. Its drain is connected to ground with a high resistance. But the transition at source is increasing the gate voltage. But I need a constant gate voltage irrespective of the transition. How can this be achieved????

Thanks in advance.

What's the root cause of the gate voltage increase when there is a fast transition on the source? I guess it is the capacitive coupling between source and gate: since the gate has a high resistance (so its voltage is not fixed), and capacitance to source and drain (maybe to some other nets as well), a fast ramp on source induces a transient voltage on gate, proportional to Cgs/Cgd (roughly speaking). The time constant of the gate transient voltage is Rg*Cgs (if drain voltage is fixed), where Rg is the gate resistance. More strictly speaking, gate network forms a distributed RC network.

So, to get rid of this parasitic transient effect, yo need to either decrease Cgs (hard to do), or increase Cgd (this might deteriorate speed of response of the transistor when you switch Vg), or decrease Rg - this is the easiest way, you can always make high resistive gate poly shorter (shorter gate finger width), and/or add more metal 1 or metal 2 to the gate network.

 

[sjamil02]

Re: PMOS voltage coupling from S-G during high V transition

Just for fruits for thought.

You should watch out for 'hot switching' since you're passing high voltage on low voltage device. Not sure what's the junction breakdown in your case.

sj