Plz help me: "internal error" during MAP process o

[Alfred_zhang]

Hi,
Now i am doing a project in ISE. In my project, there is a *.cdc file which I used to observe internal signals with chipscope later. The device I used is Vertex4.

Is there anyone encountered this problem when running ISE :
The project is successfully synthesized, then is the map process:
(information in the console)
Runing directed packing...
Runing delay_based LUT packing...
Runing timing_driven packing...
Phase1.1...
...(very long time)
Phasex.x...
Invoking physical synthesis...
........................detect an internal Error...... go to support.xilinx.com for support.

So the Error message provide no clew about the possible cause of the Error.
Is there anybody know how to deal with it? Help me, PLZ.
Thanks!

 

[echo47]

Which version ISE are you using? Have you installed the latest service pack?

An "internal error" usually means the software crashed. I've seen plenty of them. Sometimes it was a real ISE bug. Sometimes I misused an ISE feature, and it couldn't recover well enough to emit a sensible error message.

Did the errors begin right after you made a significant change to your project? Try to narrow-down the problem by temporarily removing chunks of code until the error message disappears. Yes, this can be a time-consuming process.

You mentioned a cdc file. Does it pertain to the "internal error" problem?

There may be important clues in the "....." text that you omitted.

 

[banjo]

If the design will map and route without the ChipScope stuff, but fails when you attempt to include ChipScope, then I believe you have run out of resources within the FPGA. Xilinx has had a bug where they do not correctly calculate the required resources during the synthesize phase. When it gets into MAP, it cannot place all the logic and after several phases, it crashes. The end of synthesis should report a percentage of utilization. This number can often be over 100, as some logic reduction and trimming will occur in MAP. However, if it cannot be reduced to less than 100% later, it will crash.

 

[Alfred_zhang]

Re: Plz help me: "internal error" during MAP proce

Hi, echo47 & banjo
sorry for late acknowledge.

echo47:
"Did the errors begin right after you made a significant change to your project?"
yes.

"You mentioned a cdc file. Does it pertain to the "internal error" problem? "
and banjo: "then I believe you have run out of resources within the FPGA"
Sometimes when such error happened, I deleted all the files ise produced, built the project again and did nothing but reduce the signal in cdc file. Then this error may not appear.
But now I think maybe cdc is not the cause. Because even this happened, the used blockram is 54%, it looks like resource is OK.

"There may be important clues in the "....." text that you omitted."
These "....................internal error ..........." is the real things displayed in the console.

Now I uncheck the map property "Register duplication" then no error happens. Same time I find that there is no "Invoking physical synthesis... " in the console.

 

[echo47]

I searched Xilinx for "invoking physical synthesis" and found some relevant info:
**broken link removed**
**broken link removed**

 

[Alfred_zhang]

Re: Plz help me: "internal error" during MAP proce

I searched Xilinx for "invoking physical synthesis" and found some relevant info:
**broken link removed**
**broken link removed**

Thank u very much! These two web pages are very useful.

Now I think I've found the cause of the problem.

Ps: Unchecking the "regiseter duplication" will worsen the timing of the result. Sometimes there will be timing violation in the PAR report.