[SOLVED] Please help with mc8051 core in verilog

[tuanha117@gmail.com]

I would like to run the mc8051 core supported by Oregano System with my external instruction and data memories in Verilog but the simulation runs and gives INCORRECT result at the "Post-Route" simulation event the "Behavioral" simulation gives the correct result.
(The simulation for vhdl mc8051_top module supported by Oregano System works without any problem)

Do I make some mistake in synthesis the core, the internal memory, and the external rom?

Below is my code in verilog

***********************
//Top module to combine "mc8051_core" and internal "ram" modules
//this two modules are provided by Oregano System
module mc51top(
clk, rst,
// external instruction / data memory interface
iadr_o, idata_i, adrx_o, datax_i, datax_o, wrx_o,
// ports interface
p0_i, p1_i, p2_i, p3_i, p0_o, p1_o, p2_o, p3_o,
// timer / counter interrupts
t0_i, t1_i, int0_i, int1_i,
// serial port interface
rxd_i, rxd_o, txd_o, rxd_wro
);

input clk, rst;
// instruction memory
output [15:0] iadr_o;
input [7:0] idata_i;
// external data memory
output [15:0] adrx_o;
output [7:0] datax_o;
input [7:0] datax_i;
output wrx_o;
// ports
input [7:0] p0_i, p1_i, p2_i, p3_i;
output [7:0] p0_o, p1_o, p2_o, p3_o;
// interrupts
input t0_i, t1_i, int0_i, int1_i;
// serial port intrface
input rxd_i;
output rxd_o, txd_o, rxd_wro;

// internal ram singnals
wire int_ram_wr, int_ram_en;
wire [6:0] int_ram_adr;
wire [7:0] mc51_2int_ram, int_ram_2mc51;
-------------------
mc8051_core mc51_core (
.clk(clk), .reset(rst),
// instruction memory
.rom_data_i(idata_i), .rom_adr_o(iadr_o),
// internal ram
.ram_data_i(int_ram_2mc51), .ram_data_o(mc51_2int_ram), .ram_adr_o(int_ram_adr),
.ram_wr_o(int_ram_wr), .ram_en_o(int_ram_en),
// external ram
.datax_i(datax_i), .datax_o(datax_o), .adrx_o(adrx_o), .wrx_o(wrx_o),
// ports
.p0_i(p0_i), .p1_i(p1_i), .p2_i(p2_i), .p3_i(p3_i),
.p0_o(p0_o), .p1_o(p1_o), .p2_o(p2_o), .p3_o(p3_o),
// interrupts
.int0_i(int0_i), .int1_i(int1_i), .all_t0_i(t0_i), .all_t1_i(t1_i),
// serial port
.all_rxd_i(rxd_i), .all_rxd_o(rxd_o), .all_txd_o(txd_o), all_rxdwr_o(rxdwr_o)
);
-------------------
mc8051_ram int_ram (
.clk(clk), .reset(rst),
.ram_data_i(mc51_2int_ram), .ram_data_o(int_ram_2mc51),
.ram_adr_i(int_ram_adr), .ram_wr_i(int_ram_wr), .ram_en_i(int_ram_en)
);
endmodule

***********************
//external ROM using buffer with one clock delay for the output
//the program writes FF, then 00 to port 0
module xrom (rst, clk, addr, data);
input rst, clk;
input [15:0] addr;
output [7:0] data;

reg [7:0] data;
reg [7:0] buff [0:1024]; // 1KB xrom

initial begin
$readmemh("prg.in", buff);
end

always @(posedge clk or posedge rst)
begin
if (rst) data <= buff[0];
else data <= buff [addr];
end
endmodule

***********************
//external RAM using buffer with one clock delay for the output
//the program gives no data to RAM
module xram (clk, rst, wr, addr, data_in, data_out);
input clk, wr, rst;
input [7:0] data_in;
input [15:0] addr;
output [7:0] data_out;

reg [7:0] data_out;
reg [7:0] buff [0:1024]; // 1KB xram

// write to ram
always @(posedge clk)
if (wr) buff[addr] <= data_in;

// read from ram
always @(posedge clk or posedge rst)
if (rst) data_out <= buff[0];
else data_out <= buff[addr];
endmodule

***********************
//Testbench which uses above mc8051_top, external ROM and RAM
module mc51top_tb1;
parameter one_period = 100; // 100 ns delay = 10 MHz
parameter rst_delay = one_period + one_period/2 + 5; // reset takes 155ns
parameter clk_delay = one_period/2; // clk change every 50ns
// Inputs
reg clk, rst;
wire [7:0] idata_i, datax_i;
reg [7:0] p0_i, p1_i, p2_i, p3_i;
reg t0_i, t1_i, int0_i, reg int1_i, rxd_i;
// Outputs
wire [15:0] iadr_o, adrx_o;
wire [7:0] datax_o;
wire wrx_o;
wire [7:0] p0_o, p1_o, p2_o, p3_o;
wire rxd_o, txd_o, rxd_wro;
// Instantiate the Unit Under Test (UUT)
mc51top uut (
.clk(clk), .rst(rst),
// instruction memory
.iadr_o(iadr_o), .idata_i(idata_i),
// external memory
.adrx_o(adrx_o), .datax_i(datax_i), .datax_o(datax_o), .wrx_o(wrx_o),
// ports
.p0_i(p0_i), .p1_i(p1_i), .p2_i(p2_i), .p3_i(p3_i),
.p0_o(p0_o), .p1_o(p1_o), .p2_o(p2_o), .p3_o(p3_o),
// interrupts
.t0_i(t0_i), .t1_i(t1_i), .int0_i(int0_i), .int1_i(int1_i),
// serial ports
.rxd_i(rxd_i), .rxd_o(rxd_o), .txd_o(txd_o), .rxd_wro(rxd_wro)
);

xrom xrom1(.rst(rst), .clk(clk), .addr(iadr_o), .data(idata_i));
xram xram1(.clk(clk), .rst(rst), .wr(wrx_o), .addr(adrx_o), .data_in(datax_o), .data_out(datax_i));

always #clk_delay clk = ~ clk;

initial begin
// Initialize Inputs
rst = 1'b1;
clk = 1'b0;
// ports
p0_i = 8'hff;
p1_i = 8'hff;
p2_i = 8'hff;
p3_i = 8'hff;
// interrupts
t0_i = 1'b0;
t1_i = 1'b0;
int0_i = 1'b0;
int1_i = 1'b0;
// serial in
rxd_i = 1'b0;
// Wait 155 ns for global reset to finish
#rst_delay;
rst = 1'b0;
end
endmodule