chaitanya.531
Member level 1
plz
check this code
this give no errors on xilinx but results showing uuuuuu or xxxxxx
THIS IS TEST BENCH OF A PROGRAM DECRYPTION
AND RESULTS GETTING IS
I THINK PROBLEM IN THE FILE I/O COMMNADS
file are given as attchments
PLZ HELP
check this code
this give no errors on xilinx but results showing uuuuuu or xxxxxx
THIS IS TEST BENCH OF A PROGRAM DECRYPTION
Code:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;
entity RC5_DECRYPT_TB is
generic ( T : time := 10 ns ;
infile : string := "C:\Xilinx\kcha\rc5_DECRYPT_tb.in";
outfile : string := "C:\Xilinx\kcha\rc5_DECRYPT_tb.out";
keyfile : string := "C:\Xilinx\kcha\rc5_DECRYPT_tb.key" );
end entity;
architecture test of RC5_DECRYPT_TB is
COMPONENT RC5_DECRYPT_TOP
PORT(
clk : IN std_logic;
ken : IN std_logic;
ski : IN std_logic_vector(32 downto 1);
di : IN std_logic_vector(64 downto 1);
do : OUT std_logic_vector(64 downto 1)
);
END COMPONENT;
signal clk : std_logic:='0';
signal ski : std_logic_vector(32 downto 1);
signal enable : std_logic := '0';
signal ciphertxt : std_logic_vector(32*2 downto 1);
signal plaintxt : std_logic_vector(32*2 downto 1) := (others=>'0');
file kfp : text open read_mode is keyfile;
file ifp : text open read_mode is infile;
file ofp : text open write_mode is outfile;
constant D : time := 1 ns;
begin -- architecture
uut: RC5_DECRYPT_TOP PORT MAP(
clk => clk,
ken => enable,
ski => ski,
di => ciphertxt,
do => plaintxt
);
-- process to generate clock signal
process
begin
clk <= not clk;
wait for T/2;
end process;
-- process to set up subkeys
process
variable L : line;
variable bv1 : std_logic_vector(32 downto 1);
begin
wait for 10*T;
enable <= '1' after D;
for i in 0 to 26-1 loop
readline(kfp,L); -- read subkey from file
read(L,bv1);
wait until rising_edge(clk);
ski <= bv1 after D; -- send to RC5_DECRYPT_TOP
end loop;
wait until rising_edge(clk);
enable <= '0' after D;
wait; -- halt this process
end process;
-- encrypt some ciphertxt words from the input file
process
variable L : line;
variable bv : std_logic_vector(32*2 downto 1);
begin
wait until enable='1';
wait for (26+20)*T;
while not endfile(ifp) loop
readline(ifp,L);
read(L,bv); -- read plaintext bit vector
write(L,plaintxt);
writeline(ofp,L);
wait until rising_edge(clk);
ciphertxt <= bv after D;
end loop;
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait until rising_edge(clk);
write(L,plaintxt); writeline(ofp,L);
wait;
end process;
end test;
AND RESULTS GETTING IS
I THINK PROBLEM IN THE FILE I/O COMMNADS
file are given as attchments
PLZ HELP
Attachments
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