Pickit2 clone - need help on VDD_TGT_ADJ and VDD_TGT_N/P

[secretstep]

I looked into several PicKit2 clones, but I couldn't figure out why some people people omitted the whole VDD_TGT_ADJ/VDD_TGT_N/VDD_TGT_P parts in their clones.
The problem is, I cannot really understand what those pins (pin 13, 24, 25) mean and what they are doing in the circuit.
So, can anyone help me understanding what these parts are doing from the original pickit2 schematics?



For example, from this clone, **broken link removed**
the VDD_TGT_ADJ part was omitted.

From another clone, ElectronicsADvices: VDD power delivering Pickit2
the VDD_TGT_ADJ / VDD_TGT_N / VDD_TGT_P parts were omitted.


Thank you.

 

[john blue]

That part allows you to have a variable programming voltage. The clones you mention abve omits them and only allow user to use 5V voltage supply.

 

[secretstep]

Thank you for your reply, John Blue.

Would you mind explaining in more detail to me?

For example, under what circumstances do VDD_TGT_ADJ outputs 5V or 0V?
and under what circumstances do VDD_TGT_N or VDD_TGT_P outputs 5V or 0V?
and how do they affect the target VDD (or VPP) for 5V, 3.3V, and 2.5V?

Thank you.

 

[john blue]

The user will select the PIC devices or the voltage level, the PIC18F2550 will send pwm signal to the mosftets to gain the intended voltage levels.

 

[secretstep]

Thanks.
However, I'd like to know a bit more about their operation.
Could you tell me what's the role of the VDD_TGT_N and VDD_TGT_P signals?

 

[john blue]

PIC18F2550 will control the PWM dwell time of "VDD_TGT_ADJ" output, which is integrated by capacitor C8 and resistor R4. A reference voltage is generated at the negative input (U2-pin-3) of a rail to rail operational amplifier U2. R5 and R6 is used to generate voltage feedback to positive input of U2. R7 is used to generate a small electric load and bleed the capacitor (e.g. C11 and C12) when power is turned off. MOSFET Q1 is controlled by U2 in switch mode. When "+V_TGT" is lower than the voltage PIC18F2550 set, feedback voltage on U2-pin-1 is less than voltage on U2-pin-3, the output on U2-pin-4 is Low, MOSFET Q1 will turn on, the "+V_TGT" will increase. When "+V_TGT" increased to high enough to trigger U2-pin-4 to output a High logic, Q1 will be off. When Q1 is off, the "+V_TGT" will stop rising.

 

[secretstep]

That's what I was looking for.
Thanks, John Blue.