Parity checker/decoder

[lahrach]

hi friends,

I am looking for a VHDL code of Parity checker/ decoder .

I will be nice if some one explain the parity checker Principe


best regards;

farid

 

[blacksnow]

A parity checker check the parity in the received signal on the receiver side.

e.g if 3 bit message was sent with odd parity,

a b c Parity sent
0 0 0 1 (a,b,c & parity contains odd number of 1's)
0 0 1 0
0 1 0 0
0 1 1 1 (again parity bit will be 1 to
1 0 0 0 make total number of odd 1's)
: : : :
: : : :
1 1 1 0 Parity = ((a xor b) xnor c))

if the message is sent with odd parity (odd number of 1's), then parity checker in receiving end will show error in message, if the odd number of 1's sent become even number of 1's on receiving side. i.e assume one 1 has become 0 by some means.

a b c Par sent Par check
0 0 0 0 1 (even number of 1's recived but sent
were odd number of 1's)
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
and so on.

Par check = a xnor b xnor c xnor Par sent

 

[supercat]

I am looking for a VHDL code of Parity checker/ decoder .

If the data is available simultaneously on 'n' separate wires, simply xor them all together. If the data is provided sequentially, feed it into a flip-flop whose input is (data_value) for the first bit, and (output xor data_value) for each subsequent bit.