Parameterized interface in uvm

[karalamoorthy_p]

Hi,

Shall we use parameterized interface in UVM. Actually I want to use parameterized interface in uvm top.

I am trying to use this way, but it's not working properly.

In top module I am instantiating interface like this,

a = 3; b = 1;
para_interface #(.A(a),.B(b)) para_if();

In Interface file I am using like this,

interface para_interface #(A = 2,B = 1)();
logic high[A-1:0];

In base test I am setting the interface like this,
uvm_config_db #(virtual para_interface) :: set(null,"*","sigs",top_tb.para_if);

When I do like this I am getting the following error.

uvm_config_db #(virtual rst_clk_interface)::set(null,"*","sigs",top_tb.rst_clk_if);

when I do like this I am getting the following error.
|
ncelab: *E,TYCMPAT (/home/karlamoorthy.duraipandi/accurev/SDIL-HW/SDR4/SDR4_SOC_Ver_dev/sdr4/src_env/library/tests/test_base.sv,50|84): formal and actual do not have assignment compatible data types (expecting datatype compatible with 'virtual interface rst_clk_interface#(.NO_CLK(2),.NO_RST(1))' but found an incompatible 'rst_clk_interface#(.NO_CLK(3),.NO_RST(1)) instance' instead).


Please correct if I do anything wrong.

Thanks.