NWELL_StampErrorFloat cadence

[richaphy]

Hi
I am learning to use Cadence by designing an OTA.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:

1. NWELL_StampErrorFloat
(NWELLs are highlighted)

2. Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted

3. Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted

I have connected the supply and groung to their respective connections int he nmos and pmos.

Also, just checking
Do I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?
and the bulk of the nMOS transistors to VSS, would this be the substrate?
Which means here is it necessary to provide a guard ring??
I tried the guard ring as well but even with that the error1 is still there.
Thanks

 

[erikl]

1. NWELL_StampErrorFloat (NWELLs are highlighted)

Similar to this thread's solution.

2. Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted

3. Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted

Maximum ... spacing ... is 20µm. Shouldn't this make it clear? Check your Design Rules!

I have connected the supply and groung to their respective connections int he nmos and pmos.

Good!

Do I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?

Yes!

... and the bulk of the nMOS transistors to VSS, would this be the substrate?

Yes again!

Which means here is it necessary to provide a guard ring??

No!

 

[richaphy]

Thanks for your reply.
I have attached a snapshot of the layout.
As you can see the distance between nplus and pluse diffussion is less than 2um. But still I am getting these errors.
2. Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted.
3. Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted
Also I want suggestion, I am making a design with some quiet long connection line with metal (around 50um long). What width I should choose for these line. Keeping in mind the things like parasitic like capacitance between two parallel connection metal line/wire.
Please help me to solve these issues.
Thanks

 

[rangermad]

Your errors are for n+ diff to P+ pick-up (ie bulk connection) and p+ diff to N+ pick-up. Are you LVS clean?

 

[richaphy]

I am not able to understand this bulk connection.
How can I connect bulk to ground or supply>>
Do I need to use guard ring??
Thanks

- - - Updated - - -

I think I got the answer, I have to draw a via M1 to Pactive and M1 to Nwell each for NMOS and PMOS respectively, which will be connected to ground and supply.

 

[rangermad]

Your process may have dedicated layers to use for bulk ties. If not, use p+ diff and n+ diff to connect the bulks. Just quickly throw something down in the substrate and nwell and get LVS clean. After that, work on DRCs and tidy things up to your liking.

 

[erikl]

- - - Updated - - -

I think I got the answer, I have to draw a via M1 to Pactive and M1 to Nwell each for NMOS and PMOS respectively, which will be connected to ground and supply.

Right; not a via however, but a contact. Vias are connections between metal layers.

 

[smilodon]

You should study some basic on semiconductor! Basiclly, MOS have 4 terminal include Sourece, drain, gate and bulk. As u mentioned bulk is ptap connected to psub and ntap connecnted to Nwell.

Other problerms are about DRC, you should learnt design rule firstly, and cleaned all errors.