richaphy
Member level 1
Hi
I am learning to use Cadence by designing an OTA.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:
1. NWELL_StampErrorFloat
(NWELLs are highlighted)
2. Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted
3. Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted
I have connected the supply and groung to their respective connections int he nmos and pmos.
Also, just checking
Do I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?
and the bulk of the nMOS transistors to VSS, would this be the substrate?
Which means here is it necessary to provide a guard ring??
I tried the guard ring as well but even with that the error1 is still there.
Thanks
I am learning to use Cadence by designing an OTA.
I'm a bit stuck understanding what these error messages mean in the DRC checker.
if there is a link where I can find an explanation please let me know, otherwise I'd really appreciate some help understanding the following:
1. NWELL_StampErrorFloat
(NWELLs are highlighted)
2. Maximum N+ Diffusion to nearest P+ pick-up spacing (inside P-Well or T-Well) is 20um
all nmos diffusion highlighted
3. Maximum P+ Diffusion to nearest P+ pick-up spacing (inside N-Well or T-Well) is 20um
all pmos diffusion highlighted
I have connected the supply and groung to their respective connections int he nmos and pmos.
Also, just checking
Do I need to connect the bulk of each pMOS transistor to VDD, would this be the NWEL?
and the bulk of the nMOS transistors to VSS, would this be the substrate?
Which means here is it necessary to provide a guard ring??
I tried the guard ring as well but even with that the error1 is still there.
Thanks