ananthan95
Junior Member level 3
I wrote a VHDL code for synchronous demodulation. I use vivado 2016.4. it works perfectly with a testbench in the software. but when I burnt the code into the FPGA board (Xilinx Artix-35T FPGA (xc7a35ticsg324-1L)) it doesnt work. any suggestions?
I used a software called terra term to read the output from the board. it is serial communication. nothing is wrong with the board. I tested the board with a different code and it worked. since it works fine in the simulation i couldnt find the error in my code.
the baud rate and pin mapping are double checked and verified. plus after implementing the design I ran a post-implementation timing simulation also. the result was positive. it said the user timing constraints are completely met.!! need help!
I used a software called terra term to read the output from the board. it is serial communication. nothing is wrong with the board. I tested the board with a different code and it worked. since it works fine in the simulation i couldnt find the error in my code.
the baud rate and pin mapping are double checked and verified. plus after implementing the design I ran a post-implementation timing simulation also. the result was positive. it said the user timing constraints are completely met.!! need help!