ncverilog is faster than vcs?

[gaonkc]

ncverilog is faster than vcs?

I run the simulation with same environment and test case, the ncverilog is three times faster than vcs.

What about are yours?

 

[AlexWan]

Ye,

It's true. During gate-level simulation, NC is faster than VCS visible.

Maybe the two tools use different sequence to deal with the different assignment types in simulation.

Anyone can give us a detail reason?

Thanks

 

[z81203]

Hi, which version of nc & vcs are you use?

 

[Thomson]

Ye,

It's true. During gate-level simulation, NC is faster than VCS visible.

Maybe the two tools use different sequence to deal with the different assignment types in simulation.

Anyone can give us a detail reason?

Thanks

As i know, NCVerilog is cycle-based simulator, while VCS is a event-based simulator(of course, you can use the +cycle option to enable the cycle-based functionality). Therefore if you doesn't use the VCS with the cycle option, then the simulation performance is pretty lower than the NCVerilog's.


Thomson

 

[aji_vlsi]

Hi,
I've heard that NC is some times faster than VCS for gate level and vice versa for RTL. However here are few points:

1. Both NC & VCS have cycle as well as event based algorithms - else they can't simulate any arbitrary verilog code.
2. They employ some heuristics to apply cycle/event and that might make this kind of differences.
3. During VCS run, do you see "ACC/PLI capabilities enabled for entire design" kind of message during start? If so try and fix that first - that may get you 2 to 4x speed up inside VCS.

Good Luck
Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore? Visit www.noveldv.com/cvc.html

Ye,

It's true. During gate-level simulation, NC is faster than VCS visible.

Maybe the two tools use different sequence to deal with the different assignment types in simulation.

Anyone can give us a detail reason?

Thanks

As i know, NCVerilog is cycle-based simulator, while VCS is a event-based simulator(of course, you can use the +cycle option to enable the cycle-based functionality). Therefore if you doesn't use the VCS with the cycle option, then the simulation performance is pretty lower than the NCVerilog's.


Thomson

 

[jjww110]

in rtl ,vcs is faster than nc!!

 

[gaonkc]

Hi aji_vlsi,
Can you give me a detail method to speed up the simulation time inside vcs in gate-level simulation with sdf back annotation.

Thanks,

Added after 4 hours 49 minutes:

Hi AlexWan,

The cycle option is exit?
It is not in synopsys manual.

 

[Arnold]

and you should compare these two with the latest version. I feel vcs is faster.

 

[beckchm]

vcs is slow ,so seldom use it