my first code in VHDL

[Aya2002]

Hello Friends

this is my first program with VHDL, but i faced some problems:

the code is:

21 module mysource_xor(
22 input wire in1,
23 input wire in2,
24 output wire out
25 assign out = in1 ^ in2,
26
27 );
28
29
30 endmodule
31
-----------------------------------------------------------------------
Compiling verilog file "mysource_xor.v" in library work
ERROR:HDLCompilers:26 - "mysource_xor.v" line 25 expecting ')', found 'assign'
Module <mysource_xor> compiled
Analysis of file <"mysource_xor.prj"> failed.
-->

Total memory usage is 168464 kilobytes

Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)


Process "Synthesis" failed


so, what is the error that i have done?

thank you very much

 

[devas]

Hi,

You did not write VHDL code but Verilog code.

A verilog module looks normally:

module <module name>(<i/os>);
<assignments>
endmodule;

As line 25 is an assignment, you must move it to line 28 (behind ");").

Finally an assignment line ends with a semicolon ";" instead of comma.

Success, Devas

 

[bigdogguru]

Re: my first code in HDL - Verilog

There are a couple of characters out of place, try this:

module mysource_xor(in1, in2, out);
            // Port Declarations Section
            input in1;
            input in2;
            output out;

            //Module Behavior
            assign out = in1 ^ in2;
endmodule

My Verilog is a little rusty, but I believe I caught all the syntax errors.

All ports are implicitly declared as wire.

FYI, Verilog and VHDL are both HDLs, but Verilog is not VHDL.

 

[Aya2002]

Hi,

You did not write VHDL code but Verilog code.

A verilog module looks normally:

module <module name>(<i/os>);
<assignments>
endmodule;

As line 25 is an assignment, you must move it to line 28 (behind ");").

Finally an assignment line ends with a semicolon ";" instead of comma.

Success, Devas

now i got this error:

Using target part "3s500efg320-4".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s500e' is a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:7 - A feature for ISE was found but is for the wrong hostid.
ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
'xc3s500e'.
----------------------------------------------------------------------
No such feature exists.
Feature: WebPack
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig
_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_
v10_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_v9_flexl
m.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\obsai_v3_flexlm.lic;E:\Xilinx\11.
1\ISE/coregen/core_licenses\pci32_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_
licenses\pci64_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_blk_p
lus_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_pipe_v1_flexlm.l
ic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcix_v6_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\pci_express_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/cor
e_licenses\pktq_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_lite_
v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_v8_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\pl4_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/c
ore_licenses\rio_log_io_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\r
io_log_io_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_link_v5_fl
exlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_phy_v5_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\srio_phy_v4_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\srio_phy_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_license
s\ten_gig_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ten_gig
_eth_mac_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac_v4_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\vlynq_v1_flexlm.lic;E:\Xilinx\11
.1\ISE/coregen/core_licenses\v_ccm_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core
_licenses\v_cfa_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_gamma_v
1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_ipipe_v1_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\v_rgb2ycrcb_v2_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\v_spc_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lice
nses\v_ycrcb2rgb_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v7_
flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v8_flexlm.lic;E:\Xilinx
\11.1\ISE/coregen/core_licenses\Xilinx.lic;E:\Xilinx\11.1\ISE/coregen/core_licen
ses\XilinxFree.lic;e:\Xilinx\11.1\EDK/data/core_licenses\apu_fpu_v2_flexlm.lic;[
...]
FLEXnet Licensing error:-5,357. System Error: 2 ""
For further information, refer to the FLEXnet Licensing documentation,
available at "www.acresso.com".Invalid host.
The hostid of this system does not match the hostid
specified in the license file.
Feature: ISE
Hostid: 00022ae19641
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.l
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ERROR:Map:258 - A problem was encountered attempting to get the license for this
architecture.

Design Summary
--------------
Number of errors : 1
Number of warnings : 0

Process "Map" failed

Added after 3 minutes:

There are a couple of characters out of place, try this:

module mysource_xor(in1, in2, out);
            // Port Declarations Section
            input in1;
            input in2;
            output out;

            //Module Behavior
            assign out = in1 ^ in2;
endmodule

My Verilog is a little rusty, but I believe I caught all the syntax errors.

All ports are implicitly declared as wire.

FYI, Verilog and VHDL are both HDLs, but Verilog is not VHDL.

when i have used this code i got the following message:

Reading design: mysource_xor.prj

=========================================================================
* HDL Compilation *
=========================================================================
Compiling verilog file "mysource_xor.v" in library work
Module <mysource_xor> compiled
No errors in compilation
Analysis of file <"mysource_xor.prj"> succeeded.


=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for module <mysource_xor> in library <work>.


=========================================================================
* HDL Analysis *
=========================================================================
Analyzing top module <mysource_xor>.
Module <mysource_xor> is correct for synthesis.


=========================================================================
* HDL Synthesis *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <mysource_xor>.
Related source file is "mysource_xor.v".
Found 1-bit xor2 for signal <out>.
Unit <mysource_xor> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Xors : 1
1-bit xor2 : 1

=========================================================================

=========================================================================
* Advanced HDL Synthesis *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Xors : 1
1-bit xor2 : 1

=========================================================================

=========================================================================
* Low Level Synthesis *
=========================================================================

Optimizing unit <mysource_xor> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mysource_xor, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
* Partition Report *
=========================================================================

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

=========================================================================
* Final Report *
=========================================================================

Clock Information:
------------------
No clock signals found in this design

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 6.209ns

=========================================================================

Process "Synthesis" completed successfully

Command Line: E:\Xilinx\11.1\ISE\bin\nt\unwrapped\ngdbuild.exe -ise
Test_1_XOR.ise -intstyle ise -dd _ngo -nt timestamp -i -p xc3s500e-fg320-4
mysource_xor.ngc mysource_xor.ngd

Reading NGO file "E:/Xilinx/workspace/Test_1_XOR/mysource_xor.ngc" ...
Gathering constraint information from source properties...
Done.

Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking Partitions ...

Checking expanded design ...

Partition Implementation Status
-------------------------------

No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0

Writing NGD file "mysource_xor.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec

Writing NGDBUILD log file "mysource_xor.bld"...

NGDBUILD done.

Process "Translate" completed successfully
Using target part "3s500efg320-4".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc3s500e' is a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:7 - A feature for ISE was found but is for the wrong hostid.
ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
'xc3s500e'.
----------------------------------------------------------------------
No such feature exists.
Feature: WebPack
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig
_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_
v10_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\gig_eth_pcs_pma_v9_flexl
m.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\obsai_v3_flexlm.lic;E:\Xilinx\11.
1\ISE/coregen/core_licenses\pci32_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_
licenses\pci64_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_blk_p
lus_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcie_pipe_v1_flexlm.l
ic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pcix_v6_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\pci_express_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/cor
e_licenses\pktq_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_lite_
v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\pl4_v8_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\pl4_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/c
ore_licenses\rio_log_io_v4_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\r
io_log_io_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_link_v5_fl
exlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\spi3_phy_v5_flexlm.lic;E:\Xili
nx\11.1\ISE/coregen/core_licenses\srio_phy_v4_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\srio_phy_v5_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_license
s\ten_gig_eth_mac_v8_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ten_gig
_eth_mac_v9_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\tri_mode_eth_mac_v4_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\vlynq_v1_flexlm.lic;E:\Xilinx\11
.1\ISE/coregen/core_licenses\v_ccm_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core
_licenses\v_cfa_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_gamma_v
1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\v_ipipe_v1_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\v_rgb2ycrcb_v2_flexlm.lic;E:\Xilinx\11.1\IS
E/coregen/core_licenses\v_spc_v1_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lice
nses\v_ycrcb2rgb_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v7_
flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\xaui_v8_flexlm.lic;E:\Xilinx
\11.1\ISE/coregen/core_licenses\Xilinx.lic;E:\Xilinx\11.1\ISE/coregen/core_licen
ses\XilinxFree.lic;e:\Xilinx\11.1\EDK/data/core_licenses\apu_fpu_v2_flexlm.lic;[
...]
FLEXnet Licensing error:-5,357. System Error: 2 ""
For further information, refer to the FLEXnet Licensing documentation,
available at "www.acresso.com".Invalid host.
The hostid of this system does not match the hostid
specified in the license file.
Feature: ISE
Hostid: 00022ae19641
License path:
C:/.Xilinx\webpack_adds.lic;C:/.Xilinx\xilinx11suite.lic;E:\Xilinx\11.1\ISE/data
\*.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\can_v1_flexlm.lic;E:\Xilinx\11.1
\ISE/coregen/core_licenses\can_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_lic
enses\cpri_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_stati
stics_v2_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\ethernet_statistics
_v3_flexlm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\eth_avb_endpoint_v1_flex
lm.lic;E:\Xilinx\11.1\ISE/coregen/core_licenses\fibre_channel_v3_flexlm.lic;E:\X
ilinx\11.1\ISE/coregen/core_licenses\gfp_v1_3_flexlm.lic;E:\Xilinx\11.1\ISE/core
gen/core_licenses\gfp_v2_flexlm.l
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
ERROR:Map:258 - A problem was encountered attempting to get the license for this
architecture.

Design Summary
--------------
Number of errors : 1
Number of warnings : 0

Process "Map" failed

Added after 40 seconds:

help me please

 

[bigdogguru]

Well it looks like I remembered my Verilog code fairly well.

Your module compiled without any errors, however there is a licensing issue with your ISE 11 installation. The licensing scheme for ISE 11 uses the MAC address of your ethernet port as an ID number, what they refer to as HOSTID.

FLEXnet Licensing error:-5,357. System Error: 2 ""
For further information, refer to the FLEXnet Licensing documentation,
available at "www.acresso.com".Invalid host.
The hostid of this system does not match the hostid
specified in the license file.
Feature: ISE
Hostid: 00022ae19641

Check your license file, usually just off the root directory of your main drive in a subdirectory. Open it up and make sure the HOSTID is set to 00022ae19641 which is the MAC address of your ethernet adapter. If your running windows run ipconfig, linux ifconfig in a dos or terminal window to verify.

INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.

These two environment variables point to the location of your license file, they are not currently set.

Added after 32 minutes:

It looks like you may need to get a license file. Is this a webpack installation, if so find the menu option "Manage Xilinx Licenses" under ISE, if I remember correctly it will register and retrieve a license file for you and set the environment variables to point to the location of the license file.

INFO:Security:54 - 'xc3s500e' is a WebPack part.
INFO:Security:61 - The XILINXD_LICENSE_FILE environment variable is not set.
INFO:Security:63 - The LM_LICENSE_FILE environment variable is not set.
INFO:Security:68 - Please run the Xilinx License Configuration Manager
(xlcm or "Manage Xilinx Licenses")
to assist in obtaining a license.
ERROR:Security:7 - A feature for ISE was found but is for the wrong hostid.
ERROR:Security:9 - No 'ISE' nor 'WebPack' feature was available for part
'xc3s500e'.

Also the current FPGA model is set to the Spartan 3 "3s500efg320-4" is that the correct FGPA on your development board? Also I assume you have the correct UCF also dependent on your development board.

I'm trying to recall as much of this as possible from memory, the system I'm current using does not have ISE 11 installed.

 

[Aya2002]

Ohhhhh,

I do not know, why I am facing these many problems...

My problem now is that I can't open the license manager. When I open it, immediately got an error message :




somebody help me please

 

[bigdogguru]

Let me make a suggestion. If you are just trying to simulate your Verilog code, such as the module we were troubleshooting above, download a Student copy of ModelSim:

Free Student Version of ModelSim

It's the same simulator used in Xilinx's ISE, but you do not have to deal with any hardware device selections, etc. Plus it has a fairly extensive PDF documentation.

 

[Aya2002]

is it a complete simulator, I mean, can i write codes and execute them to see the results?

Added after 16 minutes:

Done, it is installed now, but i don't know how to use it.

would you help me please as a quick stare?

Thank you

 

[bigdogguru]

ModelSim is a complete simulator, you can write VHDL or Verilog compile, debug and simulate. I have the full professional version, so there are some difference between our installations.

Go to the help menu and select documenation - PDF bookcase, once the PDF bookcase is open look for the tutorial PDF. Go ahead and work your way through the tutorial, let me know when you finish.

 

[Aya2002]

hello again,

Now i went deep through the tutorials of the modelsim. I am familiar with its environment.

Now would you help me to start programming?

how to differentiate between two codes one written by Verilog and the second by the VHDL?

thanks

Added after 17 minutes:

now, I have created a new project and wrote this code:
module mysource_xor(in1, in2, out);
// Port Declarations Section
input in1;
input in2;
output out;

//Module Behavior
assign out = in1 ^ in2;
endmodule

the output is:





My question is how to assign values to the inputs in1 and in2?

thanks

 

[FvM]

I'm sure, the tutorial mentions a testbench.

 

[Aya2002]

I'm sure, the tutorial mentions a testbench.

My Friend,

I am beginner. Would you please tell me how to create a test bench for this code?

Thanks

Added after 1 minutes:

or maybe you can show me a link to such thing.

 

[bigdogguru]

Verilog and VHDL, will both language abstraction of hardware, are as different as night and day.

Comparison of C, Verilog and VHDL

Another Comparison - PDF

Your code in Verilog:

module mysource_xor(in1, in2, out); 
      // Port Declarations Section 
      input in1; 
      input in2; 
      output out; 

      //Module Behavior 
      assign out = in1 ^ in2; 
endmodule

Your code in VHDL:

library ieee;
use ieee.std_logic_1164.all;

// Port Declarations Section 
entity vhdl_xor is
   port ( in1, in2: IN STD_LOGIC;
          out3: OUT STD_LOGIC);
end vhdl_xor ;

//Module Behavior 
architecture behavior of vhdl_xor is
begin
    
    out3 <= in1 xor in2;
      
end behavior;

Notice I had to change the output port from "out" in verilog example to "out3" in the VHDL example, because OUT is a reserve word in VHDL.

To create a simulation you need to either create a testbench or set stimuli:

**broken link removed**

I'll see what other tutorials I can find.

Added after 33 minutes:

Oddly enough it appears ModelSim removed the chapters dealing with testbench creation and stimuli from the Tutorial PDF of your version! I also checked the User Manual PDF, the information is in there but not in a very readable form.

Let me see what other tutorials I can find on testbench and stimuli creation.

 

[Aya2002]

Verilog and VHDL, will both language abstraction of hardware, are as different as night and day.

Comparison of C, Verilog and VHDL

Another Comparison - PDF

Your code in Verilog:

module mysource_xor(in1, in2, out); 
      // Port Declarations Section 
      input in1; 
      input in2; 
      output out; 

      //Module Behavior 
      assign out = in1 ^ in2; 
endmodule

Your code in VHDL:

library ieee;
use ieee.std_logic_1164.all;

// Port Declarations Section 
entity vhdl_xor is
   port ( in1, in2: IN STD_LOGIC;
          out3: OUT STD_LOGIC);
end vhdl_xor ;

//Module Behavior 
architecture behavior of vhdl_xor is
begin
    
    out3 <= in1 xor in2;
      
end behavior;

Notice I had to change the output port from "out" in verilog example to "out3" in the VHDL example, because OUT is a reserve word in VHDL.

To create a simulation you need to either create a testbench or set stimuli:

**broken link removed**

I'll see what other tutorials I can find.

Added after 33 minutes:

Oddly enough it appears ModelSim removed the chapters dealing with testbench creation and stimuli from the Tutorial PDF of your version! I also checked the User Manual PDF, the information is in there but not in a very readable form.

Let me see what other tutorials I can find on testbench and stimuli creation.

Hello Friend,

regarding your useful link to the comparison between VHDL and Verilog ( Comparison of C, Verilog and VHDL ) I found out that I have to learn VHDL and not Verilog, so that, would you help me please?

thanks

 

[bigdogguru]

Sure, Here are some VHDL Tutorials:

**broken link removed**

VHDL Tutorial: Learn by Example, Weijun Zhang - Lots of code snippets





The first tutorial is problably the most extensive, these should get you started on the road to coding in VHDL.

 

[FvM]

Would you please tell me how to create a test bench for this code?

You mentioned ModelSim tutorials before. I'm rather sure, that they are dealing with testbenches a lot, because testbenches are
a very basic concept of HDL simulation. ModelSim has special tools to generate something called a "graphical testbench" by defining
stimulus signals for the design under test interactively.

Generally, a testbench is the top design in simulation. Unlike a usual HDL module, it has no in- and output ports. A simple testbench
instantiates the design under test as its only module (Verilog) respectively component (VHDL). It's purpose is to drive the inputs
and "read" the outputs of the design. It uses simple HDL statements to generate signals. More complex testbenches read stimulus
signals from files or use additional modules to represent the behaviour of complex circuits connected to the design.

 

[bigdogguru]

Yes, I'm very familiar with ModelSim and Testbenches. I've been using ModelSim for the past three years and have generated and wrote more testbenches and "do" files than I care to admit.

However, after version 6.3x it appears that the two chapters, one dealing explicitly with testbench generation and the other with stimuli and "do" files, were removed from the tutorial! In the remaining chapters, they do show you how to run a simulation by loading a pre-existing testbench, but they never show you how to write a testbench or even explain the reason for its existence.

This makes absolutely no sense to me, as you mention, it's a critical component of using ModelSim. What is especially aggravating is the fact they had two chapters dedicated to testbenches and stimuli and they just simply removed them.

Here take a look for yourself:

**broken link removed**

Anyway I was just trying to find Aya2002 a decent tutorial on writing testbenches or a least setting up stimili manually or in "do" files. I was contemplating uploading the version 6.3f tutorial which I currently have in the lab, this appears to be the last version which included the relevent chapters which are now missing. But I'm trying not to uploading any unnecessary MBs to this forum. I'm hoping to find a link to the version 6.3x tutorial or an independent tutorial covering the material.

 

[Aya2002]

**broken link removed**

Anyway I was just trying to find Aya2002 a decent tutorial on writing testbenches or a least setting up stimili manually or in "do" files. I was contemplating uploading the version 6.3f tutorial which I currently have in the lab, this appears to be the last version which included the relevent chapters which are now missing. But I'm trying not to uploading any unnecessary MBs to this forum. I'm hoping to find a link to the version 6.3x tutorial or an independent tutorial covering the material.

Thank you very much, I have printed out this pdf document on a papers and i read it carefully but as you see it doesn't explain how to generate the test bench.

Now, do you have a document about all the commands used in the VHDL language?

also, if you have examples that showing how to execute it step by step with the test bench also how to write it and execute and write it step by step?

I know, I am bothering you because I asked you very much

Thank you very much

 

[bigdogguru]

Finally found a worthy writing testbench tutorial:

**broken link removed**

VHDLGuru's Page How to Write a Testbench



As far as VHDL standards document, listing all VHDL commands, IEEE publishes just such a PDF, however it's $200-$300 and I don't own a copy:

There are several free documents available on their website dealing with VHDL:

VHDL Search results on IEEE Website

VHDL IEEE Std. 1076-1993 Standards

I would recommend Peter J. Ashenden's Book:

The Designer's Guide to VHDL, Volume 3, Third Edition - $40

This is an exhaustive resource on VHDL, ~900 pages, I use my copy everyday.
It does contain VHDL IEEE Std. 1076-2008 which can be frustating because that standard is not fully supported by many of the software tools.

You may want to pickup a copy of the second edition, used copies available for $15.

Hope these links and comments help you in your quest!

 

[Aya2002]

I sent you two messages , please see your PM and reply me as soon as possible.

as i am waiting for you

thank you very much.