Dave_PL
Member level 2
Hi,
Ive got a module which send to me 224 bit vector. But i would like to divide this bus into 7 vectors 32 bit wide.
Now I would like to sample (7 times) in some sort of a loop like this:
where dataNumCnt (integer) = 7 at start and after every sample it is decreased by 1 (when 0 there is other condition).
Of course it works in simulation. Ive synthesize it succesfuly but Ive got a message that buff is only 32 bit wide while 224vector is 224 bit wide and Im wondering if it will work? Or is there any other solution to my problem.
Regards,
Dave
Ive got a module which send to me 224 bit vector. But i would like to divide this bus into 7 vectors 32 bit wide.
Code:
signal 224vector : std_logic_vector (223 downto 0);
signal buff : std_logic_vector (31 downto 0);
Now I would like to sample (7 times) in some sort of a loop like this:
Code:
buff <= 224vector (dataNumCnt*32 - 1 downto (dataNumCnt-1)*32);
where dataNumCnt (integer) = 7 at start and after every sample it is decreased by 1 (when 0 there is other condition).
Of course it works in simulation. Ive synthesize it succesfuly but Ive got a message that buff is only 32 bit wide while 224vector is 224 bit wide and Im wondering if it will work? Or is there any other solution to my problem.
Regards,
Dave