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Multiplexed bus problem

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Dave_PL

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Hi,

Ive got a module which send to me 224 bit vector. But i would like to divide this bus into 7 vectors 32 bit wide.

Code:
signal 224vector : std_logic_vector (223 downto 0);
signal buff : std_logic_vector (31 downto 0);

Now I would like to sample (7 times) in some sort of a loop like this:

Code:
buff <= 224vector (dataNumCnt*32 - 1 downto (dataNumCnt-1)*32);

where dataNumCnt (integer) = 7 at start and after every sample it is decreased by 1 (when 0 there is other condition).

Of course it works in simulation. Ive synthesize it succesfuly but Ive got a message that buff is only 32 bit wide while 224vector is 224 bit wide and Im wondering if it will work? Or is there any other solution to my problem.

Regards,
Dave
 

please post your other code, what you have posted doesnt tell us a lot.
 

Code:
if bitCnt < sampleRes then
    SD_O <= buff (sampleRes - bitCnt);
    bitCnt <= bitCnt + 1;
else
    SD_O <= buff (0);
    bitCnt <= 0;
    if dataNumCnt > 0 then 
	dataNumCnt <= dataNumCnt - 1;
	buff <= 224vector (dataNumCnt*32 - 1 downto (dataNumCnt-1)*32);
    else
	dataNumCnt <= 0;
	buff <= 224vector (31 downto 0);
    end if;
end if;

At the beggining inbuff is 224vector(223 downto 192) --> first 32bit sample.
 

This should work fine, but I have seen a bug with similar code to this in Quartus before. It might be best to put a case statement on dataNumCnt to be explicit with you bit selection.

Out of interest, I can see from this dataNumCnt decreases, but is never reset back to the top again. Does that happen elsewhere?
 
Yes, its a part of FSM so in other state. Saying " It might be best to put a case statement on dataNumCnt to be explicit with you bit selection." you mean sth like this:

case dataNumCnt is
when 7 => buff <= 224vector (223 downto 192);
when 6 => buff <= 224vector (191 downto 160);

etc ?
 

Yes.

Usually, instead of asking if it should work, why not try it out on your board?
 

You've got a point :)

Thank you!
 

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