nagulapatigirireddy
Newbie level 5
this is the code for converting decimal to binary in vhdl.How to cinvert a vhdl code to verilog code
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 library IEEE; use ieee.std_logic_1164.all; use IEEE.numeric_std.all; -- entity decimal is end decimal; architecture beh of decimal is signal my_sulv1 : std_ulogic_vector(15 downto 0); signal my_int : integer range 0 to 100; signal my_sulv2 : std_ulogic_vector(15 downto 0); -- begin my_int <= to_integer(unsigned(my_sulv1)); my_sulv2 <= std_ulogic_vector(to_unsigned(my_int, 16)); end beh;
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