ned_zeppelin
Newbie level 6
I know that when dealing with an asynchronous signal, synchronizing flip-flops are used to avoid metastability.
As far as I can understand, metastability is caused by the data input changing at approximately the same time
as the clock signal (of the fip-flop), thus vioalting the setup or hold time.
Now, Let's say a circuit only has one clock, named clk.
My question is this:
Should any signal generated on posedge clk, only be read on negedge clk (and vice versa)?
Or is it OK to simply read on the same clk edge and assume a 1 clk cycle delay?
In simulations the last option works fine. But my guess is that, in reality, it could result in either the "old" or "new" value being read, or metastability
possibly occuring. I really need someone with more knowledge and experience to clear this up for me, once and for all.
Any help is greatly appreciated.
As far as I can understand, metastability is caused by the data input changing at approximately the same time
as the clock signal (of the fip-flop), thus vioalting the setup or hold time.
Now, Let's say a circuit only has one clock, named clk.
My question is this:
Should any signal generated on posedge clk, only be read on negedge clk (and vice versa)?
Or is it OK to simply read on the same clk edge and assume a 1 clk cycle delay?
In simulations the last option works fine. But my guess is that, in reality, it could result in either the "old" or "new" value being read, or metastability
possibly occuring. I really need someone with more knowledge and experience to clear this up for me, once and for all.
Any help is greatly appreciated.