[SOLVED] Metastability of flip-flops within the same clock domain

[ned_zeppelin]

I know that when dealing with an asynchronous signal, synchronizing flip-flops are used to avoid metastability.
As far as I can understand, metastability is caused by the data input changing at approximately the same time
as the clock signal (of the fip-flop), thus vioalting the setup or hold time.

Now, Let's say a circuit only has one clock, named clk.

My question is this:
Should any signal generated on posedge clk, only be read on negedge clk (and vice versa)?
Or is it OK to simply read on the same clk edge and assume a 1 clk cycle delay?

In simulations the last option works fine. But my guess is that, in reality, it could result in either the "old" or "new" value being read, or metastability
possibly occuring. I really need someone with more knowledge and experience to clear this up for me, once and for all.

Any help is greatly appreciated.

 

[TrickyDicky]

Assuming all signals are generated in the same clock domain, there is no problem reading them all on the positive edge.

In FPGAs, clocks have dedicated high speed clock nets, that have extreamly low skew. The allows you to imagine that all flip-flops are clocked at the same time. This means that every signal will be stable when the edge triggers the ff, and causes it to change (or not). You need to ensure that the logic between the ffs does not take too long to change the signal, otherwise you will have metastability problems (you violate setup times. The timing analyser will tell you if this has occured).

FPGAs can only have ff triggered on positive or negative clock edges for ALL FFs, not both.

 

[ned_zeppelin]

OK. So a signal transitioning from '1' to '0' on a given posegde, is guaranteed to be read as a '1' one that specific edge (assuming that the logic seperating the FFs is minimal)?

I always assumed that allowing half a clock cycle for "settling" time was the preferred solution to any modules needing to communicate in some way. Then there wouldn't be much need for worrying about the logic between the FFs. If this is not possible on FPGAs than at least on ASICs.

I guess I may have over-estimated the dangers of metastability a little bit

 

[TrickyDicky]

remember that the transition will not actually occur at the posedge, but after the posedge. You have to ensure the transition has settled before the next posedge to make sure it's safe to read. Assuming you dont violate this, there is no problem.

This is only true for register to register connections internally to an FPGA. Going off chip, you make need to skew the clock to allow for routing delays on the PCB. I have seen people use the neg-edge in this situation, but its not really that reliable. It is much better to use a PLL with external feedback to allow it to compensate for temperature variations etc.

 

[FvM]

Synchronous logic in FPGAs and ASICS works fine with all FFs switching at the same edge. If you consider a very short fedback path, e.g. directly from a FF output back to the logic element at it's input, the delay of both elements will be already sufficient to keep the hold time requirement. To keep the setup time as well, the path delay between two FFs must be slightly shorter than a clock cycle. In other words, clocking all FFs at the same edge gives maximum headroom for logic delay, allowing e.g. arithmetical circuits cascading many logic elements.

The important prerequisite for the sketched synchronous scheme is low clock skew.

The scheme "sending and receiving on different edges" is meaningful, if low clock skew can't be guaranteed, e.g. for external interfaces.

 

[permute]

There is a setup/hold time. For logic inside a device, there will usually be a positive setup, and slightly negative hold time. this means the signal driving the FF can change slightly before the rising edge of the clock.

Some external devices can have positive setup and positive hold -- data must be stable both before and after the clock edge. Some rare devices even have negative setup and positive hold -- data can change after the clock edge, as long as it is stable for for some time after that.

For external devices, this is due to the clock and data buffers/routing being different. eg, if there is a 1ns setup 0ns hold on a FF, and you delay the clock by 1ns, then you get a 0ns setup, 1ns hold. if you instead delay the data, you get a 2ns setup -1ns hold.

The timing analysis tools try to ensure that setup/hold is met for all internal devices. Using only the positive edge, it is easiest to meet setup times. Most combinatorial logic will add delays, which helps meet hold times when there is a clock-skew. However, the tool can always try to add additional delay if needed.

 

[ned_zeppelin]

Thanks guys! Your posts really helped me out.