lhlbluesky
Banned
1.5bit/stage pipeline adc matlab
recently , i'm designing a pipelined adc with matlab simulink?
but there are some questions:
1 how to built per stage(1.5bit) use the method of transfer function?
2 how to measure the snr sndr sfdr enob inl dnl in simulink,and how to plot the in matlab?
3 if i take kt/c into acount,then what does "c" means ?the sampling cap or the total cap of per stage (if so,how to measure it)?
thanks first.
recently , i'm designing a pipelined adc with matlab simulink?
but there are some questions:
1 how to built per stage(1.5bit) use the method of transfer function?
2 how to measure the snr sndr sfdr enob inl dnl in simulink,and how to plot the in matlab?
3 if i take kt/c into acount,then what does "c" means ?the sampling cap or the total cap of per stage (if so,how to measure it)?
thanks first.