measure the gate charge(Qgs & Qgd)

[gwdbsuccess]

In order to measure the gate-source charge and the gate-drain charge of N-channel DMOS(we don't have datasheet and spice model).
Before I actually measure it,I want to simulate the BSS159N_L1 as practice in LTspice.
PMOS is used to imitate the current source.
logic level NMOS is used to imitate the switch.

I don't watch any section which like plateau region(Gate plateau voltage)

Theoretically,the Vgs-time curve should be similar as shown below
because the variation of Ig is very small in Qgs and Qgd region

if I change the NMOS & PMOS for ideal current source and ideal switch, the Vgs-time curve is right,



I don't know my circuit has problem or my simulation progress ?
Simulating file and related library files for parts is attached .
plz help me with this problem.m(_ _)m
View attachment MEASURE.rar

 

[FvM]

Instead of guessing, just look at a few more voltages and currents in your simulation and see what the problem is.

 

[gwdbsuccess]

1.change NMOS for ideal switch

the trend of curve doesn't change.


2.change right side PMOS for ideal current source

the curve have some variation as shown below.

but the current of gate isn't costant in plateau region(Qgd region)


3.from above step,change left side PMOS for ideal current source

it still have the same problem as above




On the problem of 2 & 3,I still have no ideal.