vipul982
Junior Member level 3
Hi,
I want to assess the following condition:
If an MBIST controller and memory is intended to run at a functional frequency say 100MHz and a testbench is also generated to run at same frequency, but the frequency that is recieved is 20MHz. How will the failure look like in simulation?
1. will there be a DONE failure indicating a test did not complete?
2. Will the test run and indicate a DONE & GO failure?
Thanks,
Vip
I want to assess the following condition:
If an MBIST controller and memory is intended to run at a functional frequency say 100MHz and a testbench is also generated to run at same frequency, but the frequency that is recieved is 20MHz. How will the failure look like in simulation?
1. will there be a DONE failure indicating a test did not complete?
2. Will the test run and indicate a DONE & GO failure?
Thanks,
Vip