Low Voltage(1.2v) CMOS bandgap design

[cretu]

cmos bandgap design

Hi,

is there anybody that can give me some info for a bandgap/current mirror deisgn in deep sub-micron cmos? I need something for a project. I need bascaly any ideas that can work for a current mirror with +/- 5% variation of the replicated currents

I should mention that I need to bias the tail of a current-mode logic cmos D latch

 

[BigBoss]

design of low-voltage bandgap

This one is good starting point being as initial.

 

[tlihu]

cmos bandgap without bipolar device

"A CMOS Bandgap Reference Circuit w/ Sub-1-V Operation," IEEE JSSC Vol. 34 No. 5 May 1999 pp. 670-674

 

[electronrancher]

chartered spice model

+/- 5% is hard enough to get in minimum-length submicron - hope you're not using min-len mirrors!

i suggest the roncon-mora book "voltage references, from diodes to precision hi-order bandgap circuit" if you want to know HOW to build low voltage gaps. else google search (or citeseer search) for IEEE papers if you just need an example..
-er

 

[andy2000a]

design of a cmos bandgap reference in 0.35

how about BJT model in CMOS process ??
BJT is parastic device in CMOS analog design ,

in real design case , I design a bandgap circuit in Chartered_Fab
and get 1000 pcs sample , I find some problem

hspice simulation have error on bandgap voltage
simulation is 1.2v
but measure all sample focus on 1.22v , it have 20mV error
chartered_Fab said , it is OK .. becuase BJT is parastic device
in CMOS ...

How do you think it ??

another problem is in submicro CMOS process , How to make sure
Bandgap design can meet "hspice simulation "
which spice model parameter will effect BJT performance ?
beta ? because Beta is very small ...
include temp ... or corner model , some FAB only Typ model
no BJT corner model ..

If no shuttl chip can test it , how to make sure first cut design is OK
on bandgap voltage ? like battery chip need more accuracy voltage
and bias current , as I know
bandgap voltage still have large variation on process ...

 

[Humungus]

bandgap 1.2v

If instead of 1.2V you got 1.22, this means that the error is not random. I mean, if it was caused by devise mismatch, you wouldn't have gotten with a certain spread.

In bandgap design it is very important the characterization of diodes. What you have to do is make an indeep characterization of the diodes (parasitic transistors or whatever). You must try to determine if sending again your design to the fab, you would get 1.22V again or not. If the obtained values would vary from 1.22V, the you can deduce that your devices have too much lot variation.

If, conversely, you got about 1.22V, then you can say that process is OK and that precision is just a mater of improving your models.

Anyway, if you use a current mode bandgap, as the output voltage is a current (almost constant with temperature) multiplied by a resistance, you can preview some resistor taps or transistors in your current mirror to recenter your design once it has been produced. So, by measuring a small quantity of your samples you can determine which tap to bond in all remaining samples in order to get your ouput voltage recentered.

After that, total spread only depends on matching:
* use large devices
* reduce offsets (random and systematic)
* use well fitted models
* try to give you some opportunity for die tunning.

 

[andy2000a]

cmos bandgap 1.2v

Hi
Thank you for advise ..

I use chartered provide BJT model & BJT Gds layout ...
in many wafer lot be measure , I can said chartered process is focus on
1.22v ... so process is accuracy , but the problem is hspice model not
fit to this process , when I ask a accuracy model , chartered said
"this Logic process , if you need it , you must design test key and
measure by yourself .."

I can overcome simulation unmatch after try many time tape/out ,
but I have one question is how to get real model ?
I know someone use "poly fuse or metal_fuse" , but this device is low
cost , it can not use this method .. my boss said ask me , why the simulation model VS. real chip have this difference ..

and I can use another size BJT device , becuase chartered only this type device ( tsmc have pnp10 pnp20 .., but chartered not) , I don't know
which bandgap circuit architerutre can recovery this problem ...
maybe some bandgap circuit can make this effect small ..

If FAB provider BJT model is not accuracy , how can I make bandgap design is ok . ---> this is my really problem , don't tell me try by error ,
or try by next wafer

I want to know why TSMC have more accuracy model but chartered not .
which parameter can control BJT performance ?

 

[hardings]

current mode bandgap bjt

Why not fix the model by yourself?

For Vbe, I think you can calculate the parameter IS using the process

data.

And compare what you get and the data in the model.

 

[shiowjyh]

simulation pnp10 tsmc

Hello,

Have you ever simulate the corner cases?
I might believe the corner deviation should be considered.
(Please also note that TSxx provide corner bipolar model if process goes down to 0.25um. 0.35um does not.)
Second, check the temperature sweep, though bandgap should be insensitive to temp.
Third, I am not quit sure which process you are going for,
But one thing could be sure of is there are two or more emitter area available for cmos bipolar.
And can you imagine the simulation results are??
Final thing to be considered is the device mismatch...

Comments:
If you do really need an accurate bandgap, then go for pure SiGe bipolar instead.
Or I heard about a EDA vendor introduce a spice model of level 88,
Which can also improve the accuracy. However, it seems not a free charge.

For your reference,

Regards,

 

[andy2000a]

cmos bandgap

Hello,

Have you ever simulate the corner cases?
---> sorry , Chxxx 0.35um process no corner model for BJT model
(3 year ago condition ...)

I might believe the corner deviation should be considered.
(Please also note that TSxx provide corner bipolar model if process goes down to 0.25um. 0.35um does not.)
Second, check the temperature sweep, though bandgap should be insensitive to temp.

--> yes , I simulation temperate is ok

Third, I am not quit sure which process you are going for,
But one thing could be sure of is there are two or more emitter area available for cmos bipolar.

---> I use 0.35um CMOS process , only one type pnp device

And can you imagine the simulation results are??
Final thing to be considered is the device mismatch...

--> after try by next wafer out , I fix this problem ...
but I question is hspice simulation bandgap with real chip , which tolerance can be said ok ?? the FAB said simulation & real_chip have
20mv offset , it is ok ...

but , I don't know .. maybe anothers FABs TXXX or UXX only have small offset on bandgap design ...

who can tell me TXXX UXXX or
china new Fabs like 中芯國際(SMIC)、宏力(GSMC)、先進(ASMC)
和上海華虹NEC



thank you

 

[sunjimmy]

low voltage bandgap

Hi, Humungus,

Could you kindly show me some papers or articles regarding to the current mode bandgap ?

Is it possible to realize this current mode bandgap via generic CMOS process with parasitic PNP device ?

Thanks a lot for your answer in advance : )

 

[sunjimmy]

Hi, Humungus,

Could you kindly show me some papers or articles regarding to the current mode bandgap ?

Is it possible to realize this current mode bandgap via generic CMOS process with parasitic PNP device ?

Thanks a lot for your answer in advance : )

 

[Humungus]

HI,

I'm on vacation right now, so I don't have access to the papers, but you can make a search using low voltage bandgap.

You can use any type of bipolar device.

Regards

Humungus

 

[SwordFish]

maybe you can use this....

 

[legend]

Hello,
this is a good paper for your problem.

 

[yellff]

This is 0.13um's refence .than how about 90nm?