tarjina
Junior Member level 3
Hello everyone,
I am doing my thesis work on developing a design methodology which reduces the post layout simulation time for large analog designs.
I cannot find a proper literature that already talks about it. Whenever I search I get articles, books on Analog verification, mixed-signal verification, algorithms for verification but no-one speaks about the reducing run-time. If anyone can direct me to a one single literature regarding this, I would be really happy.
I am on a clock and kind of stuck!
Thanks in advance!!
I am doing my thesis work on developing a design methodology which reduces the post layout simulation time for large analog designs.
I cannot find a proper literature that already talks about it. Whenever I search I get articles, books on Analog verification, mixed-signal verification, algorithms for verification but no-one speaks about the reducing run-time. If anyone can direct me to a one single literature regarding this, I would be really happy.
I am on a clock and kind of stuck!
Thanks in advance!!