LDNMOS ESD Improve ??

[mark_nctu]

ldnmos

My IC uses a open drain LDNMOS for output. The Vout.max is 20V and
core circuit is 5V system. The ESD testing was fail when OUT-VCC+ and
OUT-VSS+ zapped (only 500V). How to improve ESD ?

Thanks

 

[IanP]

Connect bidirectional transient voltage suppressor (≈ +/-30V) between output and 0V ..

 

[shrbht]

is that possible to integrate SCR structure in LDNMOS?

 

[DoctorProf]

Do you have any protection currently on the output? If not then it sounds like the LDNMOS can not self protect. You will need to add protection.

As one other person suggested you could add a clamp (i.e. SCR) on the drain but unless you know details about the process you might not be able to desgin an SCR the first time that would have the correct trigger and holding voltage. You might see if the process you are using has any high voltage diodes that breakdown at higher voltage than your operating voltage but lower than the LDNMOS. You would size the diode large enough to handle the required ESD current and provide a low enough resistance so the voltage does not get too high and cause the LDNMOS to breakdown.

You could try ballasting the output device by placing a poly resistor in each drain finger of the device. It is best to us the largest poly resistor you can affort (from an Rdson standpoint). Make the width of each finger small and have a lot of fingers and the parallel combination of resistors will allow a larger value per finger.

Hope this helps.

Dr. Prof