[SOLVED] How to improve my DAC design to get an appropriate output

[mohamis288]

Hello,
I have designed a circuit like this:

This is a R-2R DAC. lower transistors in each arm, are used to connecting the arm to real ground and virtual ground. those which are connected to virtual ground made up our DAC output. control voltages are outputs of 8-bit ADC and its output voltage is between 1.2 and -1.2 . but cadence gives warning:

Warning from spectre at time = 250.502 us during transient analysis `tran'.
    WARNING (CMI-2682): M0: The bulk-drain junction forward bias voltage (797.149 mV) exceeds `VjdmFwd' = 793.148 mV.  The results are now incorrect because the junction current model has been linearized
Warning from spectre at time = 250.502 us during transient analysis `tran'.
    WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (794.799 mV) exceeds `VjdmFwd' = 793.148 mV.  The results are now incorrect because the junction current model has been linearized
Warning from spectre at time = 250.502 us during transient analysis `tran'.
    WARNING (CMI-2682): M6: The bulk-drain junction forward bias voltage (793.641 mV) exceeds `VjdmFwd' = 793.148 mV.  The results are now incorrect because the junction current model has been linearized
Notice from spectre at time = 250.502 us during transient analysis `tran'.
    M6: The bulk-drain junction returns to normal bias condition
Notice from spectre at time = 250.502 us during transient analysis `tran'.
    M5: The bulk-drain junction returns to normal bias condition
Notice from spectre at time = 250.502 us during transient analysis `tran'.
    M0: The bulk-drain junction returns to normal bias condition
Warning from spectre at time = 375.502 us during transient analysis `tran'.
    WARNING (CMI-2682): M0: The bulk-drain junction forward bias voltage (798.932 mV) exceeds `VjdmFwd' = 793.148 mV.  The results are now incorrect because the junction current model has been linearized
Warning from spectre at time = 375.502 us during transient analysis `tran'.
    WARNING (CMI-2682): M5: The bulk-drain junction forward bias voltage (794.957 mV) exceeds `VjdmFwd' = 793.148 mV.  The results are now incorrect because the junction current model has been linearized
        Further occurrences of this warning will be suppressed.
Notice from spectre at time = 375.502 us during transient analysis `tran'.
    M5: The bulk-drain junction returns to normal bias condition
Notice from spectre at time = 375.502 us during transient analysis `tran'.
    M0: The bulk-drain junction returns to normal bias condition
        Further occurrences of this notice will be suppressed.

Both clock and input signal to ideal ADC which provides our control voltage are "vpulse" functions. the output would be like this which is not acceptable:

what is the problem?
any help would be appreciated.

 

[dick_freebird]

I don't like the look of that "DAC". The "resistors" are not
resistors (MOSFETs biased into conduction, expect much
nonlinearity), the virtual-ground point is not shown, the
settling time is going to suck because you're hard-banging
the current sinks and their reference rail (ought to be
"steering" current with as much finesse as practical) and
how do you figure on keeping the "R" matched when every
stage has a different Vgs (common "vb" along a varyingly-
biased ladder)?

The source of the complaints is likely the conflict between M0
with its B, S to "fk" (check yourself, not practical on a basic
one-well JI CMOS flow) and drain-commoned to M59 with its
B, S grounded. Any positive-going signal on "fk" will forward
bias M0 D-B. because both sides of this "pair" are co-driven
(b0). And you'll be pushing "fk" directly into Psub! if it's indeed
a cheapo JI flow (you will find the ERC / LVS errors later).