is there is any tool convert state diagram to systemverilog?

[THUNDERRr]

how to convert state diagram to hdl?

is there is any tool convert state diagram to systemverilog?

 

[boardlanguage]

state disgram in vhdl

is there is any tool convert state diagram to systemverilog?

I don't know about Systemverilog, but for VHDL and Verilog, there are plenty of State-diagram (graphic) editors. All of them let you enter/edit diagrams on the screen, then write-out a VHDL/Verilog RTL description.

(The Verilog version will compile in any Systemverilog compiler, as long as don't use Systemverilog keywords in your state-diagram's signal/port names.)

<edit>

Opps, I forgot to say WHERE to find those editors, haha.
Xilinx Webpack comes with a state-diagram editor.
I'm pretty sure Altera Quartus II Web-edition comes with one, too.

If you don't want to download such big packages, then get the Aldec Student Edition Active-HDL 7.2.

Aldec Active-HDL 7.2 comes with a nice "VHDL -> state-diagram" converter utility. It converts Verilog/VHDL coded state-diagrams (i.e. written out as RTL), back into a graphical state-diagram. (Sadly, it doesn't work for Systemverilog -- I tried.)

All of these tools are free downloads from www.xilinx.com, www.altera.com, www.aldec.com