[SOLVED] IP core (Verilog or VHDL code) in Xilinx and Vivado are open source or encrypted?

[stackprogramer]

IP core (Verilog or VHDL code) in Xilinx and Vivado is open source or encrypted?
I had a question how much I can determine whether the IP core is encrypted or Verilog code is open to editing?
I attached an IP core that is built in the synthesis can you guide me that this IP core source is open?
I was faced with some strange lines. Is this IP core source encrytped?

`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2019.1"
`protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eD8hpFSXjd1TN/qwD6KGU+z2509uzOtDyaItcj8UJV6/9IqXwmzXm49sQewLHmPx+zfD6FQpyw+p
h0cjnBe4og==

`protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-2", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
L3SB3aFsPoBeCHEa+GJTxCywCdtSUeC6UY906VBmK5CfzTgqgVyM79kYm6BdXD2tikY3hMRbv08+
R63jVwCpRcJdeLJIbr58+pkInrN5jPNeOMVT4fdRP6mG/A+kbgolgF+LCX4UlGa6A14h5xUJIQ+I
BOJCodJ7zf2U3UPN5i4=

`protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IDpiTi+KiM/mIyaieWhkLwbuAoWvynL5XwxHTZc9uzTfzudCoilyQ4oKu2/PRnV4HtTBM1PW4epl
rd9LP+loq5H8NbcXKhoN4VzhEypgVleSbFixkcTkk7Osf7hVTnIQPy+t0WVEWaONYL5atSlOleSA
iLuTn53tMAhqoF+UIInXe7RC0RJ3+CAVLKs9w091HN93vVUPCig/wIe/MmVL56SzFtGO/87XTi/+
qJFEM7WvagMWeW2rwVCOs/gjJhh8s+7tB2d3KXQb0D4ZLH7wYYzzwMxpSMKY/l9qmmdLA/pN12/C
iPZ8yl6wlb49sIPVnHi7OqJQ2eGqj1d8h/GCTA==

...

 

[barry]

Does this look like Verilog or VHDL to you? Do you see the line that says “Xilinx Encryption Tool”? What do you think that means?

 

[stackprogramer]

Please download attached file the source ip core is verilog and vhdl....

 

[kaz1]

As you were told it is all encrypted though some files are given extension like vhd or v.
It is obvious they are not vhd or verilog (I blame xilinx for such silly naming)

 

[ads-ee]

Please download attached file the source ip core is verilog and vhdl....

Did you even bother to look at any of the VHDL files in the IP directories? If you had spent 30 seconds opening the files one at a time you would have seen all the design files are encrypted.

BTW, it took longer to download and unzip the archive than it took to look through all the HDL files to see if they were all encrypted (other than a testbench and some wrapper files).

--- Updated Mar 30, 2022 ---

As you were told it is all encrypted though some files are given extension like vhd or v.
It is obvious they are not vhd or verilog (I blame xilinx for such silly naming)

They are VHDL or verilog...they are encrypted, if you have the decryption key and the decryption algorithm you can convert them to clear text. That is what the vendor tools do (simulators, synthesis, etc).

 

[stackprogramer]

Did you even bother to look at any of the VHDL files in the IP directories? If you had spent 30 seconds opening the files one at a time you would have seen all the design files are encrypted.

BTW, it took longer to download and unzip the archive than it took to look through all the HDL files to see if they were all encrypted (other than a testbench and some wrapper files).

--- Updated Mar 30, 2022 ---

They are VHDL or verilog...they are encrypted, if you have the decryption key and the decryption algorithm you can convert them to clear text. That is what the vendor tools do (simulators, synthesis, etc).

@ads-ee @kaz1 @barry yes, I am a newbie for FPGA, and for the assurance, I asked. thanks very much