inout port problem vhdl testbench

[gautamvsharma]

Hi All,

i have a problem, while i am driving my INOUT pin named "reset" of testbench(vhdl) connected with my TOP LEVEL(vhdl) which has one module generating clock and reset for all fpga modules and I/Os.

The problem is while i am trying to drive the pin by generated local stimulus(Obviously..!! i have one reference signal to drive INOUT pin for both in and out mode that is "DCM locked output" mapped to TP_A7_tb in my testbench code) through testbench, it is generating some metastable state for some clocks, and then DCM locked output suddenly goes down,

the sample code is written here,

entity tb_top
end tb_top;

...
...
...
--Generation of local reset, TP_A7_tb is locked output from DCM.
rst_process rocess
begin
wait until (TP_A7_tb = '0');
MRSET_tb <= '1';
wait for 0.5 ms;
MRSET_tb <= '0';
wait for 0.5 ms;
MRSET_tb <= '1';
wait for 0.5 ms;
MRSET_tb <= '0';
wait for 0.5 ms;
MRSET_tb <= '1';
wait until (TP_A7_tb = '1');
wait;
end process;

process(GCLK_P)
begin
if (GCLK_P = '1') then
tmp_flag1 <= tmp_flag;
tmp_flag2 <= tmp_flag1;
tmp_flag <= TP_A7_tb;
end if;
end process;

process(tmp_flag2,tb_rst_out)
begin
if (tmp_flag2 = '1') then
tb_rst_in <= tb_rst_out;
else
tb_rst_in <= 'Z';
end if;
end process;

process(MRSET_tb,tmp_flag2)
begin
if (tmp_flag2 = '0') then
tb_rst_out <= MRSET_tb;
else
tb_rst_out <= 'Z';
end if;
end process;


i have instantiate IOBUF in my top level vhdl code, which is communicating with testbench stimulus is given as below,

IOBUF_inst : IOBUF
generic map (
DRIVE => 12,
IOSTANDARD => "LVTTL",
SLEW => "SLOW")
port map (
O => temp_reset, -- Buffer output--Connected to DCM--"ACTUAL DESIRED DESIGN INPUT WHICH REQUIRES CONCENTRATION"
IO => MRSET_NP, -- Buffer inout port (connect directly to top-level port)--Connected with TESTBENCH
I => ext_rst_out_ns, -- Buffer input--TOP LEVEL MODULE RESET OUT
T => inv_locked_top_ns); -- 3-state enable input, high=input, low=output--Tri state output (inverted DCM locked).


--
--

Please suggest be what shall i do to come up with more optimum result. the wave form of metastable stage is also attached with this thread.

My expectation is, temp_reset signal mentioned in IOBUF should be glitch and metastable stage free, and it should not reset DCM again(as it is doing in current design).

Thanks in advance.

 

[TrickyDicky]

that doesnt look like meta stable to me.It looks like you're not driving 'Z' in time and both ends are driving at the same time for a short period.

 

[std_match]

It is impossible to see metastability in simulation. It happens only in the real world.

 

[gautamvsharma]

that doesnt look like meta stable to me.It looks like you're not driving 'Z' in time and both ends are driving at the same time for a short period.

Hi TrickyDicky,

It seems like metastable to me, because it is not in either state, and the second thing, as if you refer the code, than you can see, i have described the correct driving statement for Z and process generated reset signal mapped to "tb_tst_out". I resolved the issue temporary, and now i can see the simulation without metastability.

But for sure, this was very tricky to drive from testbench.

Please also suggest me, how to handle bidirectional busses from/to testbench and RTL.