bhatnidhibhat
Newbie level 3
Hi all,
This is the very old problem which is already discussed in this board. But still i didn't get the clear understanding. Please help me in this regard. I have written a verilog code for one of the bi-directional IO cell. It contains one core input A, one control pin CNTL, one inout pin Y and one output pin Z. Here Y will be operated both in driver mode and receiver mode.
When CNTL=0, A will be input and Y will be output. And Z will follow the Y.
When CNTL=1, driver will be disabled. i.e. through bufif0 i will make Y to tri-state.
In this case i want to use Y as a input and drive Z.
This is the simple and brief functionality of my IO cell. Now i want to write a verilog test bench for this code. I need to test it for both driver mode and receiver modes in single test bench.
Please let me know how to declare Y pin in tb and how to give the input to Y?
--
Shrinidhi.
This is the very old problem which is already discussed in this board. But still i didn't get the clear understanding. Please help me in this regard. I have written a verilog code for one of the bi-directional IO cell. It contains one core input A, one control pin CNTL, one inout pin Y and one output pin Z. Here Y will be operated both in driver mode and receiver mode.
When CNTL=0, A will be input and Y will be output. And Z will follow the Y.
When CNTL=1, driver will be disabled. i.e. through bufif0 i will make Y to tri-state.
In this case i want to use Y as a input and drive Z.
This is the simple and brief functionality of my IO cell. Now i want to write a verilog test bench for this code. I need to test it for both driver mode and receiver modes in single test bench.
Please let me know how to declare Y pin in tb and how to give the input to Y?
--
Shrinidhi.