include problem...please help

[syedshan]

Hello all

I am including a file into verilog code.
I am using Xilinx ISE .The rtl code is just fine after I add the include path in synthesis option and did the following...

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
module icnd();
parameter zero = 0;
parameter one = 1'b1;
 
task increament;
input clk,rst;
output [3:0] count;
 
begin
    if(rst) count <= zero;
    else count <= count + one;
end
endtask
 
endmodule

---

then my top level module is following

^^^^^^^^^^^^^^^^

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
include "icnd.v"
 
module count(
    input clk,rst
    output reg [3:0] count );
 
always@(posedge clk)
begin
icnd.increament(clk,rst,count);
end
 
endmodule

---

using <include file>.<module> it completely works fine.
But the same thing when simulating, posts an error...
Although still in the test bench I am adding the include file path to the option as well `include "icnd.v" as well in beginning of simulation file

The error is as follows
:HDLCompiler:687 - "icnd.v" Line 3: Illegal redeclaration of module <icnd>.

Kindly help me how to simulate this type of code ( in which the file is included externally, though RTL is working fine)

 

[krishna2728]

Re: `include problem...please help

To enable the file in your ’include statement to be recognized, identify the directory in
which it resides, either to ISE® Design Suite or to XST.
• Since ISE Design Suite searches the project directory by default, adding the file to
your project directory identifies the file to ISE Design Suite.
• To direct ISE Design Suite to a different directory, include a path (relative or
absolute) in the ’includestatement in the HDL source code.
• To point XST directly to your include file directory, use Verilog Include Directories
(-vlgincdir)
• If the include file is required for ISE Design Suite to construct the design hierarchy,
this file must either reside in the project directory, or be referenced by a relative or
absolute path. The file need not be added to the project.
The XST design project file provides another way to make a Verilog file contents visible
to the rest of your project. Xilinx® recommends the XST design project file method. If you
use the file inclusion method, be aware of a potential conflict. Do not include a Verilog
file with the mechanism described here, and, at the same time, list that file in your XST
design project file. Doing so results in an error as follows:
ERROR:HDLCompiler:687 - "include_sub.v" Line 1: Illegal redeclaration of module <sub>.
You may encounter this error if you add Verilog files with such inclusions to an ISE
Design Suite project. Because ISE Design Suite adds them to the XST design project file,
a multiple-definition conflict can result.

 

[syedshan]

Re: `include problem...please help

Thank you for your reply,

I have included the file and tried all the ways but the error persist unfortunately.
What I did was that I also include the file to the test bench as well. But now the error shown in image appears...
I have added the path to the synthesis options. Because of which only I was able to synthesize my design, Only I cannot simulate it using ISIM (My modelsim does not work at all so I am using ISIM)

Thank you in advance



Regards,
Shan

 

[krishna2728]

your code: module count(input clk,rst output reg [3:0] count );


please try module count(input clk,rst , output reg [3:0] count );



i have run this code and got no errors after modification

 

[syedshan]

Thank you Krishna for your reply.
I had a printing mistake because of which a comma was left...
My synthesis working but simulation not working.
Following is my simulation file as well... It will not take much time if you just test it... If you get time... I am getting following error :

Line 9: increament is not declared under prefix icnd

The simulation code is as below

`include "icnd.v"

module test;

	// Inputs
	reg clk;
	reg rst;

	// Outputs
	wire [3:0] count;
	//wire [3:0] count1;

	// Instantiate the Unit Under Test (UUT)
	count uut (	.clk(clk), 	.rst(rst),.count(count)	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		#40 rst =0;
	end
      
		always #5 clk=~clk;

endmodule

 

[manojkhandelwal]

Hi,

its really confusing what is your icnd.v ?
is it the one which has module count or module icnd?
may be i can help if u give clear info...

Thanks,
Manoj

 

[syedshan]

Dear Thank you for response.

icnd.v is the module that has my task and I am calling that task in my top-level module. As you can see task increament below

module icnd();

parameter zero = 0;
parameter one = 1'b1;
 

task increament;
input clk,rst;
output [3:0] count;
 
begin
    if(rst) count <= zero;
    else count <= count + one;
end
endtask
 
endmodule

Now I have also included this file to my test bench as well but still I am getting the same error. Following is my test bench as well

`include "icnd.v"

module test;

	// Inputs
	reg clk;
	reg rst;

	// Outputs
	wire [3:0] count;
	//wire [3:0] count1;

	// Instantiate the Unit Under Test (UUT)
	count uut (	.clk(clk), 	.rst(rst),.count(count)	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 1;
		#40 rst =0;
	end
      
		always #5 clk=~clk;

endmodule

 

[manojkhandelwal]

Hi,
post your icnd.v also

Thanks
Manoj

 

[permute]

I had done something like this a long time ago.

Verilog has tranditionally worked like this:
concat all files -- synthesize -- implement.
In fact, one of the common issues for my Verilog lab was getting errors on "module", because there was a missing "endmodule" in a different file! I think more modern synthesizers pick up this case as an error within the correct file.

C/C++ places includes in every file. This breaks the traditional Verilog flow because a module will be defined several times.
to fix this, either remove the "header" includes:

// don't include anything, just add the files to the project

or use `ifndef and `define (which is also common in C/C++). eg:

`ifndef MY_MODULE_VH
  `include "my_module.vh"
  `define MY_MODULE_VH
`endif

This will cause the module to be loaded one time. IIRC, ISE will do the correct thing if you select only the top module -- it will import the others into the project. However it may (it's been a long time) have issues if you try to add all files to the project, as each file will try to re-add based on the includes.

This same issue occurs with `define -- it is possible to forget a `define and "inherit" a previous declaration from another file!

for these reasons, verilog headers often contain just `define and other similar statements. This also helps when doing simulations, as the simulator might be given only one file to compile at a time.

 

[syedshan]

Hi,

icnd.v is already there. The first code...! the second is testbench while in the beginnig of the thread is top level module as well

 

[manojkhandelwal]

Hi,

in the test bench you did not include the file which contains your top module "count" ...
you have included "icnd.v" which is not your top module, and doesent contain module "count"
It should give error for module instantiation itself....

Thanks,
Manoj