in pipeline ADC where two-stage OTAs are implemented,cap value each stage determine?

[hsiangleung]

in conventional pipeline ADC design, usually single-stage OTA is used whose noise contribution can be expressed directly associated with the sampling and feedback capacitors of each stage. In a two-stage OTA, because of miller or cascode compensation, OTA noise contribution is directly related to the compensation capacitor,Cc, rather than the sampling and feedback capacitors of each stage. Then how can we choose the value of sampling/feedback capacitors of each stage according to the noise constraints. Can any one help? thanks very much.

 

[erikl]

Re: cap values

Sampling caps: as low as possible; lower limit given by the input RC constant to load the sampling caps to the necessary accuracy corresponding to your ADC's resolution, during the given sampling time (e.g. 7*RC for 10bit resolution). And in any case at least a few (3..10) times larger than the OTA's input capacitance (to achieve the required gain).

Make Cc as low as possible for the adjusted gain, but to keep still enough PM to avoid excessive ringing for your sample frequency.

 

[hsiangleung]

Re: cap values

many thanks for your suggestions! I'll try it.

Sampling caps: as low as possible; lower limit given by the input RC constant to load the sampling caps to the necessary accuracy corresponding to your ADC's resolution, during the given sampling time (e.g. 7*RC for 10bit resolution). And in any case at least a few (3..10) times larger than the OTA's input capacitance (to achieve the required gain).

Make Cc as low as possible for the adjusted gain, but to keep still enough PM to avoid excessive ringing for your sample frequency.