Adding jitter to an ideal delta-sigma ADC implemented in cadence

[Javad1991]

Dear friends,

I have designed a continuous-time bandpass delta-sigma converter in cadence using ideal components.
As you know, these types of circuits include both analog (continuous-time) and digital (discrete-time) blocks.

I am trying to simulate the effect of jitter in my design. The problem is that all the digital blocks are ideal and respond fast (without rise or fall time) and are jitter-free.
In MATLAB Simulink, it's easy. I can open the loop and add a simple block, whose name is "band limited white noise" to my design, but how can I do the same in cadence virtuoso?

P.S. : It is not a good idea to add two inverters to the signal path, because it will only add rise/fall times and, of course, delay to my sigma-delta loop and is not equivalent to true jitter with a gaussian distribution!

As always, I look forward to hearing your ideas.
Many thanks

 

[dick_freebird]

You might like a veriloga widget that starts as a simple delay, ant then make that delay cycle-by-cycle bounded-pseudorandom. This could give you random jitter. But if you are interested in DJ (which can produce "tones" / spurs) then you need the mechanisms and stimuli / couplings to "get real". My only experience with this is after the fact, find out why and fix; predicting is a way bigger, unfocused adventure with no way to gauge result until fab-out.

 

[Dominik Przyborowski]

Add noise to components?