Given the exact same two files above with the change of the entity name of the 2nd to lat_reg. I got the following consistent results from two different synthesis tools: XST and Vivado synthesis (I believe for both of these, the core synthesis technology was purchased by Xilinx).I must confess, I never noticed this before. In both Quartus versions, I get the below results by including or excluding the data input in the sensitivity list. I don't think that the behaviour corresponds to the VHDL LRM. I'm also not yet aware of a synthesis attribute controlling the automatic latch to dff conversion.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity lat is port( enable: in std_logic; Output: out std_logic; Input: in std_logic); end; architecture behavioral of lat is begin -- Infers a latch process (enable, input) is begin if enable = '1' then output <= input; end if; end process; end;
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity lat is port( enable: in std_logic; Output: out std_logic; Input: in std_logic); end; architecture behavioral of lat is begin -- Unexpectedly infers a synchronous register process (enable) is begin if enable = '1' then output <= input; end if; end process; end;
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Vivado 2014.3.1
lat:
![lat_vivado_2014.3.1.PNG lat_vivado_2014.3.1.PNG](https://www.edaboard.com/data/attachments/48/48331-623cf705dbe962220bc7184c53034d06.jpg)
lat_reg:
![lat_reg_vivado_2014.3.1.PNG lat_reg_vivado_2014.3.1.PNG](https://www.edaboard.com/data/attachments/48/48332-e4686197408a6082ea97ebc8e68541bd.jpg)
lat_reg warnings
![lat_reg_warnings_vivado_2014.3.1.PNG lat_reg_warnings_vivado_2014.3.1.PNG](https://www.edaboard.com/data/attachments/48/48335-f6ae43ea1c336081f260472140b349c8.jpg)
ISE 14.7
lat:
![lat_ise_14.7.PNG lat_ise_14.7.PNG](https://www.edaboard.com/data/attachments/48/48334-abe6f083455a992e23878f9992b6e7b3.jpg)
lat_reg:
![lat_reg_ise_14.7.PNG lat_reg_ise_14.7.PNG](https://www.edaboard.com/data/attachments/48/48336-973b8b9984cabcbdf18e2091e7bc9433.jpg)
lat_reg warnings
![lat_reg_warnings_ise_14.7.PNG lat_reg_warnings_ise_14.7.PNG](https://www.edaboard.com/data/attachments/48/48333-2f3dceb6b4beb595e1ee0e66f34be0dd.jpg)
Currently I don't have Synplify installed so I can't check its results.
So the question remains, which tool is doing the correct synthesis? ISE and Vivado both think the description is a poorly written latch as it seems to expect that a register has to have an edge controlled event.