hoangthanhtung
Full Member level 3
iscas benchmark
I heard that if you want to test a new standard cell (area, power, delay ...), everybody should use ISCAS benchmark circuits (see site: **broken link removed**)
If I design a set of standard cell (OR, INV, NAND ...) in full-custom design, how can I test my logic gates with ISCAS benchmark ?
If anybody has some example or document, please upload for me
Best regards
I heard that if you want to test a new standard cell (area, power, delay ...), everybody should use ISCAS benchmark circuits (see site: **broken link removed**)
If I design a set of standard cell (OR, INV, NAND ...) in full-custom design, how can I test my logic gates with ISCAS benchmark ?
If anybody has some example or document, please upload for me
Best regards