How to perform a dither archi for 1-bit sigma-delta adc?

[castrader]

How to generate random code?

How to define dither voltage level?

I know that dither level is about LSB/2, I want to know how to get this level.

Can anyone give me some advice or architecture or papers?

Also can anyone tell me when design it, what need I take care mostly?

Thank you very much!

 

[FvM]

Schreyer discusses the topic in detail in his books on SD data converters.

 

[xwcwc1234]

What is the book name of "Schreyer" ?

 

[amir81]

generally, you can design a random (or pseudo random) sequence generator. you can vary the length of shift register to achieve better results. then add it to your modulator to make your signal busy enough.

 

[Alan_Nesta]

take care not let quantizer overloading

 

[castrader]

I am afraid if dither is too large to keep quantizer overloading, how to select dither amplitude?

 

[rfsystem]

A SD modulator with 1-bit output and n-bit input could be controlled by an additional 1bit-dither input. Because the mean value of the dither sequence is 0.5 a systematic difference exist. For audio application it is not important.